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ryan.arnold pushed a commit to branch releases/linaro-4.9-2015.05 in repository toolchain/release-notes.

commit 004d0fd9897ed72f932f05b2645f9e95454bf94f Author: Ryan S. Arnold ryan.arnold@linaro.org Date: Wed Jul 22 23:14:47 2015 -0500

Create release notes for release linaro-4.9-2015.05. --- components/toolchain/gcc-linaro/4.9/README.textile | 32 ++++++++++++++++++---- 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/components/toolchain/gcc-linaro/4.9/README.textile b/components/toolch [...] index d398ebf..1045a08 100644 --- a/components/toolchain/gcc-linaro/4.9/README.textile +++ b/components/toolchain/gcc-linaro/4.9/README.textile @@ -1,13 +1,33 @@ -p. The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.06 re [...] +p. The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.05 Qu [...]

-p. Linaro GCC 4.9 2015.06 is the thirteenth Linaro GCC source package release in t [...] - -p. With the imminent release of ARMv8 hardware and the recent release of the GCC 4 [...] +p. Linaro GCC 4.9 2015.05 is the second Linaro GCC 4.9 series source package quart [...]

h4. Interesting changes in this GCC source package release include:

-* Linaro bugzilla PR fixed : #849, #1599 -* Updates to GCC 4.9.3-pre+svn225109 +* Added configure-time option for Cortex-A32 erratum 843419 workaround. +* Linaro bugzilla PR fixed: #415, #1382, #1391 +* Updates to GCC 4.9.3-pre+svn222035 +* Backport of instruction scheduler improvements +* Backport of [AArch64,Neon] Add patterns + builtins for vld[234](q?)_lane_* intrinsics +* Backport of [AArch64] Implement fusion adrp+add/movk+movk +* Backport of [AArch32] Cortex-A17 support +* Backport of [AArch64] Fix __builtin_aarch64_absdi, must not fold to ABS_EXPR +* Backport of PR rtl-optimization/63917 +* Backport of PR tree-optimization/62178 tree-ssa-loop-ivopts +* Backport of [AArch64] Add TARGET_MIN_DIVISIONS_FOR_RECIP_MUL +* Backport of [AArch64] Simplify patterns for sshr_n_[us]64 intrinsic +* Backport of [AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic +* Backport of [AArch32] Fix reservation pattern in cortex-a9-neon.md +* Backport of [AArch64] Don't disparage add/sub in SIMD registers +* Backport of [AArch64] Add SIMD-reg variants of logical operators and/ior/xor/not +* Backport of [AArch64] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON +* Backport of [AArch32] Use Cortex-A17 tuning parameters for Cortex-A12 +* Backport of [AArch32] Make CLZ_DEFINED_VALUE_AT_ZERO and CTZ_DEFINED_VALUE_AT_ZE [...] +* Backport of [AArch32] Minor optimization on thumb2 tail call +* Backport of [AArch64] Update APM/XGene-1 +* Backport of [AArch64] Add a new scheduling description for the ARM Cortex-A57 processor +* Backport of [AArch64] Fix PR 64263: Do not try to split constants when destinati [...] +* Backport of [AArch64] Add support for -mcpu=cortex-a72

h4. Feedback and Support