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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/llvm-master-aarch64-spec2k6-O2_LTO in repository toolchain/ci/llvm-project.

from bdea88325f7 Fix MSVC "result of 32-bit shift implicitly converted to 64 [...] adds 045b0f60b61 [NFC] Added more tests for D63652 adds c90de6375e7 [asan] Avoid two compiler-synthesized calls to memset & memcpy adds 999f676d755 [OpenCL][PR41963] Add generic addr space to old atomics in [...] adds 96e77ce626a [X86] isBinOp - move commutative ops to isCommutativeBinOp. NFCI. adds dbcdad51ff8 [InstCombine] (1 << (C - x)) -> ((1 << C) >> x) if C is bit [...] adds bdf7f81b89d [AMDGPU] hazard recognizer for fp atomic to s_denorm_mode adds 8f25a021dd1 [AArch64][GlobalISel] Make s8 and s16 G_CONSTANTs legal. adds 0da13ed1f67 [DAGCombine] narrowExtractedVectorBinOp - pull out repeated [...] adds 08b2bd0f30f [asan] Quote the path to the Python exe in case it has spaces adds 4c9def4a51a Ensure that top-level QualType objects also have a "kind" f [...] adds 6af1be96641 [X86] Use vmovq for v4i64/v4f64/v8i64/v8f64 vzmovl. adds 0f21507b447 [OPENMP]Fix PR42068: Vla type is not captured. adds 5a701712c03 Fix ARM buildbot. adds f4836172568 [InstCombine] add tests for ctpop folds; NFC adds 2441a4074c1 [NFC] Update shl-sub tests adds 5698921be2d [SLP] Look-ahead operand reordering heuristic. adds fe4625fb248 [GlobalISel][IRTranslator] Change switch table translation [...] adds 6e71b34fe69 [AArch64][GlobalISel] Implement selection support for the n [...] adds b250a62a51b Quote path to Python executable in case it has spaces adds 459f733ef00 [clang-scan-deps] print the dependencies to stdout and remo [...] adds e4956d2ec62 Revert [test][Driver] Fix Clang :: Driver/cl-response-file.c adds 5dba4ed2082 [X86][AVX] Combine INSERT_SUBVECTOR(SRC0, EXTRACT_SUBVECTOR [...] adds ce6c06dfdd8 [X86] Add a debug print of the node in the default case for [...] adds 91ea99295ce [X86] Add avx512bw command lines to avx512-select.ll adds 4569cdbcf55 [X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless [...] adds 410b650e674 Implement P0340R3: Make 'underlying_type' SFINAE-friendly. [...] adds 4649a051bf0 [X86] Add DAG combine to turn (vzmovl (insert_subvector und [...] adds 7f9c9f22642 [Target] Decouple ObjCLanguageRuntime from LanguageRuntime adds 22e3dc60a00 AMDGPU: Fix not using s33 for scratch wave offset in kernels adds 405c2b16225 Devirtualize destructor of final class. adds f5a5785632d [X86] Add test cases for incorrect shrinking of volatile ve [...] adds 5050a8da189 Fix __has_cpp_attribute expansion to produce trailing L and [...] adds 979ae80af7e PR42301: Abort cleanly if we encounter a huge source file r [...] adds 67d1f8ae6d9 clang-format a block; NFC adds 19c4d660f45 [ASan] Use dynamic shadow on 32-bit iOS and simulators adds eeb3f99d23c [clang-tidy] misc-unused-parameters: don't comment out para [...] adds 6442317219f [llvm-lipo] Implement -thin adds fa52674ac08 Fix has_attribute.cpp test on Windows after r364102 adds 36176249d13 Ensure Target Features always_inline error happens in C++ cases. adds a9bfda08ca9 Remove binary finally accidentially committed in r364109 adds 592a193285c Revert [SLP] Look-ahead operand reordering heuristic. adds 1c6fc7d70d4 [lit] Make lit-lldb-init configurable by CMake adds 892f022ec2b [lit] Deduplicate logic in toolchain.py adds 51a741c87fa Add new style meta-programming primatives. adds 7ecb5145bae [COFF, ARM64] Fix encoding of debugtrap for Windows adds 21f0f717067 gn build: Merge r364046. adds 4608868d2f4 AArch64: Prefer FP-relative debug locations in HWASANified [...] adds 0eb966c8248 [llvm-objdump] Move --start-address >= --stop-address check [...] adds 82df97ca8e6 [ODRHash] Skip some typedef types. adds c900c46d77f [NFC] Marking test added in r363975 as unsupported on Windows. adds 4a2a1524906 [llvm-objdump] Allow --disassemble-functions to take demang [...] adds 3df71e05370 Fix UNSUPPORTED attribute from windows to system-windows. adds fc84925208e AMDGPU: Fix target builtins for gfx10 adds 43e14390b02 Make GlobalISel depend on SelectionDAG after D63169 adds 01d649c2495 [CMake] Delete redundant DEPENDS/LINK_LIBS from LineEditor/XRay adds 8cd780b432d AArch64: Add support for reading pc using llvm.read_register. adds ed78daf810a [X86] Don't use _MM_FROUND_CUR_DIRECTION in the intrinsics tests. adds b89d7e52dbc [LFTR] Add tests for PR41998; NFC adds e96fda726e8 [NewGVN] Remove dead SwitchEdges variable; NFC adds 8c8e40f763f [NewGVN] Fix copy/paste mistake in cast adds ae02f6b594e PDB docs: Delete trailing whitespace, wrap to 80 cols adds d801cb1f548 [PowerPC][NFC] Move comment to the relevant function adds 6f3222ed94f [NFC] Fix indentation in PPCAsmPrinter.cpp adds a5b83bc9e3b [CommandLine] Remove OptionCategory and SubCommand caches f [...] adds 8deb84c8ef8 Exploit a zero LoopExit count to eliminate loop exits adds a962c1bc0fd [X86][SSE] Fold extract_subvector(vselect(x,y,z),0) -> vsel [...] adds ebae85bc4a3 builtins: relax __iso_volatile_{load,store}32 adds d050479be51 Natural MSVC visualization of constructors adds 780c374b205 Remove reliance on toCharUnitsFromBits rounding down. adds 1fa07ebd929 Fix TBAA representation for zero-sized fields and unnamed b [...] adds 64b0924531c Revert [CommandLine] Remove OptionCategory and SubCommand c [...] adds bc85dbe2ba7 Disable -Wignored-attributes for now adds 5f4ae7c4571 [Support] Fix build under Emscripten adds 2a31c9ba677 Fix placement of -Wno-ignored-attributes adds 08c699a1105 MSVC visualizers for type aliases adds cf92a1f6eb1 Add noexcept throughout <atomic> adds 6281ccea02d Revert "builtins: relax __iso_volatile_{load,store}32" adds de2b633a4a0 Add super fast _IsSame trait for internal use. adds 8d7924560ea Disable test by default adds cadd826d0af [X86][SelectionDAG] Cleanup and simplify masked_load/masked [...] adds 6ddc7912b0e [SelectionDAG] Remove the code that attempts to calculate t [...] adds 6620e3b2f69 SlotIndexes: simplify IdxMBBPair operators adds 13a5ae58fcf [InstCombine] squash is-power-of-2 that uses ctpop adds f955d5f623d SlotIndexes: delete unused functions adds d22a2a9a726 [IndVars] Remove dead instructions after folding trivial loop exit adds 3f8264b0628 [Tests] Autogen and improve test readability adds 9bc3141dc2d Fix test for 32-bit targets. adds c8d94e78899 [X86] Fix isel pattern that was looking for a bitcasted loa [...] adds e2291f5af92 Fix typo in comment; NFC adds 3359a17b3ae Apply new meta-programming traits throughout the library. adds fb2bd4a9398 Use C++11 implementation of unique_ptr in C++03. adds c6094f0495b [GN] Generation failure caused by trailing space in file name adds e8da65c698e [X86] Turn v16i16->v16i8 truncate+store into a any_extend+t [...] adds 2fb6b0f2baf [ELF][PPC][X86] Use [-2**(n-1), 2**n) to check overflows fo [...] adds 9771f500f29 PR42362: Fix auto deduction of template parameter packs fro [...] adds 8c1b73591fa [llvm-readobj/llvm-readelf] - Eliminate the elf-groups.x86_ [...] adds a94c18fc200 Follow up of rL363913. NFC. adds bb6d0b8e7b0 [Support] Fix error handling in DataExtractor::get[US]LEB128 adds a5bb7b6c20e [libcxx] [test] Read files as bytestrings to fix py3 encodi [...] adds 3519d5535a4 [docs][llvm-nm] Improve symbol code documentation adds fe8017621ea [ARM] Add MVE interleaving load/store family. adds 853dfab799f [OpenCL] Remove more duplicates from opencl-c.h adds b502a44110f [OpenCL] Restore ATOMIC_VAR_INIT adds 078d711908a [sancov] Avoid unnecessary unique_ptr adds 2c5ff946277 [docs][llvm-nm] Add missing options to documentation adds 512b1187794 [Scalarizer] Add scalarizer support for smul.fix.sat adds 485a421876d [ConstantFolding] Use hasVectorInstrinsicScalarOpd. NFC adds 69144a925e7 [DAGCombine] visitMUL - allow shift by zero in MulByConstant. adds ca89eb5f9c9 [clangd] Improve SelectionTree string representation adds b617b0808de [InstCombine] SliceUpIllegalIntegerPHI - bail on out of ran [...] adds 942404d01b7 AMDGPU: Cleanup checking when spills need emergency slots adds 15e678e8438 [CUDA][HIP] Don't set comdat attribute for CUDA device stub [...] adds f27f794d473 [InstCombine] add tests for funnel-shift to bswap; NFC adds 60957cb74c8 AMDGPU: Fold frame index into MUBUF adds 5dbd9228c44 AMDGPU/GlobalISel: Fix RegBankSelect for s1 sext/zext/anyext adds 89efefb170e [InstCombine] reduce funnel-shift i16 X, X, 8 to bswap X adds 2bc35b79380 Hexagon: Rename Register class adds db26bcda8cb [OPENMP]Relax the test checks to pacify 32bit buildbots, NFC. adds 3260ef16bbd [AMDGPU] Remove unused variable AllSGPRSpilledToVGPRs. NFC adds e3a676e9adb CodeGen: Introduce a class for registers adds 906d494b6e7 [analyzer] Fix JSON dumps for ExplodedNodes

No new revisions were added by this update.

Summary of changes: .../clang-tidy/misc/UnusedParametersCheck.cpp | 13 +- clang-tools-extra/clangd/Selection.cpp | 13 +- .../test/clang-tidy/empty-database.cpp | 2 + .../test/clang-tidy/misc-unused-parameters.c | 2 +- clang-tools-extra/test/lit.cfg.py | 16 +- clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 + clang/include/clang/Frontend/Utils.h | 3 + clang/lib/AST/JSONNodeDumper.cpp | 1 + clang/lib/AST/ODRHash.cpp | 45 ++ clang/lib/Basic/SourceManager.cpp | 25 + clang/lib/Basic/Targets/AMDGPU.cpp | 2 + clang/lib/CodeGen/CGCall.cpp | 10 + clang/lib/CodeGen/CGExpr.cpp | 11 - clang/lib/CodeGen/CGExprCXX.cpp | 30 +- clang/lib/CodeGen/CGExprConstant.cpp | 3 +- clang/lib/CodeGen/CodeGenFunction.cpp | 11 +- clang/lib/CodeGen/CodeGenFunction.h | 1 + clang/lib/CodeGen/CodeGenModule.cpp | 5 + clang/lib/CodeGen/CodeGenTBAA.cpp | 4 + clang/lib/Frontend/DependencyFile.cpp | 4 + clang/lib/Headers/opencl-c-base.h | 7 +- clang/lib/Headers/opencl-c.h | 74 ++- clang/lib/Lex/PPMacroExpansion.cpp | 12 +- clang/lib/Sema/SemaExpr.cpp | 40 +- clang/lib/Sema/SemaTemplate.cpp | 5 +- clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 8 +- clang/test/AST/ast-dump-types-json.cpp | 72 +++ clang/test/Analysis/dump_egraph.c | 12 +- clang/test/ClangScanDeps/Inputs/regular_cdb.json | 6 +- clang/test/ClangScanDeps/regular_cdb.cpp | 31 +- clang/test/CodeGen/avx512dq-builtins.c | 24 +- clang/test/CodeGen/avx512er-builtins.c | 60 +- clang/test/CodeGen/avx512f-builtins.c | 688 ++++++++++----------- clang/test/CodeGen/avx512vl-builtins.c | 8 +- clang/test/CodeGen/tbaa-struct.cpp | 8 +- clang/test/CodeGen/tbaa.cpp | 8 +- clang/test/CodeGenCXX/devirtualize-dtor-final.cpp | 23 + clang/test/CodeGenCXX/no-unique-address.cpp | 16 + clang/test/CodeGenCXX/tail-padding.cpp | 16 +- clang/test/CodeGenCXX/target-features-error.cpp | 17 + clang/test/CodeGenOpenCL/amdgpu-features.cl | 6 +- clang/test/CodeGenOpenCL/builtins-amdgcn-ci.cl | 1 + .../builtins-amdgcn-dl-insts-err-clamp.cl | 1 + .../CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl | 1 + .../test/CodeGenOpenCL/builtins-amdgcn-dl-insts.cl | 2 + clang/test/CodeGenOpenCL/builtins-amdgcn-gfx9.cl | 1 + clang/test/CodeGenOpenCL/builtins-amdgcn-vi.cl | 3 + clang/test/Driver/cl-response-file.c | 2 +- clang/test/Headers/opencl-c-header.cl | 12 + clang/test/Modules/odr_hash.cpp | 63 +- clang/test/OpenMP/parallel_codegen.cpp | 22 +- clang/test/Preprocessor/has_attribute.cpp | 152 ++--- clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp | 15 + clang/tools/clang-scan-deps/ClangScanDeps.cpp | 65 +- clang/utils/ClangVisualizers/clang.natvis | 58 +- compiler-rt/lib/asan/asan_globals.cc | 7 +- compiler-rt/lib/asan/asan_mapping.h | 16 +- compiler-rt/lib/sanitizer_common/sanitizer_mac.cc | 38 +- .../sanitizer_common/sanitizer_symbolizer_win.cc | 3 + compiler-rt/test/asan/lit.cfg | 12 +- libcxx/CMakeLists.txt | 4 +- libcxx/include/__tuple | 2 +- libcxx/include/atomic | 56 +- libcxx/include/cmath | 2 +- libcxx/include/functional | 6 +- libcxx/include/math.h | 74 +-- libcxx/include/memory | 208 ++----- libcxx/include/optional | 101 +-- libcxx/include/tuple | 52 +- libcxx/include/type_traits | 295 ++++----- .../libcxx/type_traits/lazy_metafunctions.pass.cpp | 58 +- .../test/libcxx/utilities/meta/meta_base.pass.cpp | 91 +++ .../meta/stress_tests/stress_test_is_same.sh.cpp | 57 ++ .../stress_tests/stress_test_metafunctions.sh.cpp | 67 ++ .../meta.trans.other/underlying_type.fail.cpp | 38 ++ .../meta.trans.other/underlying_type.pass.cpp | 88 ++- .../unique.ptr.ctor/pointer_deleter.fail.cpp | 4 - libcxx/utils/libcxx/test/format.py | 14 +- lld/ELF/Arch/PPC.cpp | 3 + lld/ELF/Arch/PPC64.cpp | 12 +- lld/ELF/Arch/X86_64.cpp | 4 +- lld/ELF/Target.h | 2 +- lld/test/ELF/Inputs/i386-reloc-16-error.s | 3 - lld/test/ELF/Inputs/i386-reloc-16.s | 3 - lld/test/ELF/Inputs/i386-reloc-8-error.s | 3 - lld/test/ELF/Inputs/i386-reloc-8.s | 3 - lld/test/ELF/Inputs/x86-64-reloc-16-error.s | 3 - lld/test/ELF/Inputs/x86-64-reloc-16.s | 3 - lld/test/ELF/Inputs/x86-64-reloc-8-error.s | 3 - lld/test/ELF/Inputs/x86-64-reloc-8.s | 3 - lld/test/ELF/aarch64-abs16.s | 8 +- lld/test/ELF/aarch64-abs32.s | 8 +- lld/test/ELF/aarch64-prel16.s | 4 +- lld/test/ELF/aarch64-prel32.s | 4 +- lld/test/ELF/i386-reloc-16.s | 27 +- lld/test/ELF/i386-reloc-8.s | 27 +- lld/test/ELF/ppc32-reloc-addr.s | 10 +- lld/test/ELF/ppc64-addr16-error.s | 13 - lld/test/ELF/ppc64-reloc-addr.s | 25 + lld/test/ELF/x86-64-reloc-16.s | 14 - lld/test/ELF/x86-64-reloc-8-16.s | 25 + lld/test/ELF/x86-64-reloc-8.s | 14 - lldb/include/lldb/Breakpoint/Breakpoint.h | 25 +- .../lldb/Breakpoint/BreakpointPrecondition.h | 30 + lldb/include/lldb/Core/PluginManager.h | 12 +- lldb/include/lldb/Target/LanguageRuntime.h | 5 +- lldb/include/lldb/Target/ObjCLanguageRuntime.h | 7 +- lldb/include/lldb/lldb-forward.h | 2 + lldb/include/lldb/lldb-private-interfaces.h | 3 + lldb/lit/CMakeLists.txt | 4 + lldb/lit/helper/toolchain.py | 10 +- lldb/lit/{lit-lldb-init => lit-lldb-init.in} | 0 lldb/source/Breakpoint/Breakpoint.cpp | 16 +- lldb/source/Breakpoint/BreakpointPrecondition.cpp | 26 + lldb/source/Breakpoint/CMakeLists.txt | 1 + lldb/source/Core/PluginManager.cpp | 14 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV1.cpp | 3 +- .../ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp | 3 +- lldb/source/Target/LanguageRuntime.cpp | 37 +- lldb/source/Target/ObjCLanguageRuntime.cpp | 12 + lldb/source/Target/Target.cpp | 4 +- llvm/docs/CommandGuide/llvm-nm.rst | 197 ++++-- llvm/docs/PDB/HashTable.rst | 10 +- llvm/docs/PDB/ModiStream.rst | 12 +- llvm/docs/PDB/MsfFile.rst | 24 +- llvm/docs/PDB/TpiStream.rst | 94 +-- llvm/docs/PDB/index.rst | 18 +- llvm/include/llvm/Analysis/VectorUtils.h | 9 +- .../include/llvm/CodeGen/GlobalISel/CallLowering.h | 14 +- .../include/llvm/CodeGen/GlobalISel/IRTranslator.h | 82 ++- .../GlobalISel/LegalizationArtifactCombiner.h | 51 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 22 +- .../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 2 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 22 +- llvm/include/llvm/CodeGen/MachineOperand.h | 5 +- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 6 +- llvm/include/llvm/CodeGen/Register.h | 60 ++ llvm/include/llvm/CodeGen/SlotIndexes.h | 75 +-- .../include/llvm/CodeGen/SwiftErrorValueTracking.h | 9 +- llvm/include/llvm/CodeGen/SwitchLoweringUtils.h | 30 +- llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 2 +- llvm/include/llvm/CodeGen/VirtRegMap.h | 4 +- llvm/include/llvm/Target/TargetSelectionDAG.td | 4 +- llvm/lib/Analysis/ConstantFolding.cpp | 29 +- llvm/lib/Analysis/VectorUtils.cpp | 10 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 6 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 550 +++++++++++++--- llvm/lib/CodeGen/GlobalISel/LLVMBuild.txt | 2 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 122 ++-- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 26 +- llvm/lib/CodeGen/LiveDebugValues.cpp | 4 +- llvm/lib/CodeGen/MachineOperand.cpp | 2 +- llvm/lib/CodeGen/MachineRegisterInfo.cpp | 6 +- llvm/lib/CodeGen/RegAllocGreedy.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 31 +- .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 16 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 2 +- llvm/lib/CodeGen/SlotIndexes.cpp | 17 +- llvm/lib/CodeGen/SwiftErrorValueTracking.cpp | 6 +- llvm/lib/CodeGen/SwitchLoweringUtils.cpp | 1 + llvm/lib/CodeGen/TargetInstrInfo.cpp | 6 +- llvm/lib/LineEditor/CMakeLists.txt | 1 - llvm/lib/Support/DataExtractor.cpp | 28 +- llvm/lib/Support/Unix/Path.inc | 3 + llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 10 +- llvm/lib/Target/AArch64/AArch64CallLowering.h | 8 +- llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp | 6 +- llvm/lib/Target/AArch64/AArch64FastISel.cpp | 8 + llvm/lib/Target/AArch64/AArch64FrameLowering.cpp | 19 +- llvm/lib/Target/AArch64/AArch64FrameLowering.h | 4 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 8 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 + .../Target/AArch64/AArch64InstructionSelector.cpp | 63 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 11 +- .../AArch64/AArch64RedundantCopyElimination.cpp | 4 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 8 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h | 6 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 114 +++- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 3 +- llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/BUFInstructions.td | 23 +- llvm/lib/Target/AMDGPU/FLATInstructions.td | 18 +- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp | 41 ++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h | 1 + llvm/lib/Target/AMDGPU/MIMGInstructions.td | 2 + llvm/lib/Target/AMDGPU/R600Packetizer.cpp | 4 +- llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/R600RegisterInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIDefines.h | 5 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 54 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 19 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 18 +- llvm/lib/Target/AMDGPU/SIInstrFormats.td | 5 + llvm/lib/Target/AMDGPU/SIInstrInfo.h | 13 + llvm/lib/Target/AMDGPU/SIInstrInfo.td | 37 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 10 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 2 +- llvm/lib/Target/ARC/ARCOptAddrMode.cpp | 2 +- llvm/lib/Target/ARC/ARCRegisterInfo.cpp | 4 +- llvm/lib/Target/ARC/ARCRegisterInfo.h | 2 +- llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMBaseRegisterInfo.h | 2 +- llvm/lib/Target/ARM/ARMCallLowering.cpp | 24 +- llvm/lib/Target/ARM/ARMCallLowering.h | 6 +- llvm/lib/Target/ARM/ARMInstrMVE.td | 134 ++++ llvm/lib/Target/ARM/ARMInstrThumb2.td | 4 +- llvm/lib/Target/ARM/ARMRegisterInfo.td | 9 - llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 105 +++- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 36 ++ .../lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp | 14 + llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h | 3 + llvm/lib/Target/BPF/BPFRegisterInfo.cpp | 2 +- llvm/lib/Target/BPF/BPFRegisterInfo.h | 2 +- llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 66 +- llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonRegisterInfo.h | 2 +- llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp | 4 +- llvm/lib/Target/Lanai/LanaiRegisterInfo.h | 4 +- llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp | 2 +- llvm/lib/Target/MSP430/MSP430RegisterInfo.h | 2 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 66 +- llvm/lib/Target/Mips/MipsCallLowering.h | 18 +- llvm/lib/Target/Mips/MipsRegisterInfo.cpp | 2 +- llvm/lib/Target/Mips/MipsRegisterInfo.h | 2 +- llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 16 +- llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp | 2 +- llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h | 2 +- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 2 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 108 ++-- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 104 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 16 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 4 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 4 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVRegisterInfo.h | 2 +- llvm/lib/Target/Sparc/SparcRegisterInfo.cpp | 2 +- llvm/lib/Target/Sparc/SparcRegisterInfo.h | 2 +- llvm/lib/Target/SystemZ/SystemZElimCompare.cpp | 6 +- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 54 +- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 8 +- llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp | 6 +- llvm/lib/Target/SystemZ/SystemZRegisterInfo.h | 2 +- .../Target/WebAssembly/WebAssemblyRegisterInfo.cpp | 4 +- .../Target/WebAssembly/WebAssemblyRegisterInfo.h | 2 +- llvm/lib/Target/X86/X86CallLowering.cpp | 16 +- llvm/lib/Target/X86/X86CallLowering.h | 6 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 20 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 85 ++- llvm/lib/Target/X86/X86InstrAVX512.td | 131 ++-- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 62 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 6 +- llvm/lib/Target/X86/X86InstrSSE.td | 62 +- llvm/lib/Target/X86/X86RegisterInfo.cpp | 2 +- llvm/lib/Target/X86/X86RegisterInfo.h | 2 +- llvm/lib/Target/XCore/XCoreRegisterInfo.cpp | 4 +- llvm/lib/Target/XCore/XCoreRegisterInfo.h | 2 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 23 + .../Transforms/InstCombine/InstCombineCalls.cpp | 7 + llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp | 5 + .../Transforms/InstCombine/InstCombineShifts.cpp | 8 + .../Instrumentation/AddressSanitizer.cpp | 12 +- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 20 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 6 +- llvm/lib/XRay/CMakeLists.txt | 8 - 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