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from 51e5a5cefb1 RISC-V: Support RVV VFMACC rounding mode intrinsic API new 4d8b5563179 AArch64: Avoid the ICE on empty reduction definition in inf [...] new 62d9c1dd8eb RISC-V: Support RVV VFNMACC rounding mode intrinsic API

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Summary of changes: gcc/config/aarch64/aarch64.cc | 2 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 24 +++++++++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/testsuite/gcc.target/aarch64/pr110625_3.c | 35 ++++++++++++++++ .../base/float-point-single-negate-multiply-add.c | 47 ++++++++++++++++++++++ 6 files changed, 110 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/pr110625_3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-nega [...]