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from 74b8757 Take code ownership of LLVM bitcode. new 884f3fe [sancov] specifying comdat for sancov constructors new 7914168 [AMDGPU] Implement register pressure callbacks new 063022b GlobalISel: expand mul-with-overflow into mul-hi on AArch64. new e1ee35e GlobalISel: select G_[SU]MULH on AArch64.

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Summary of changes: include/llvm/Target/GenericOpcodes.td | 18 +++++++++++++ include/llvm/Target/TargetOpcodes.def | 8 ++++++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 27 +++++++++++++++++++ lib/Target/AArch64/AArch64InstructionSelector.cpp | 28 +++++++++++++++++++ lib/Target/AArch64/AArch64LegalizerInfo.cpp | 5 +++- lib/Target/AMDGPU/SIRegisterInfo.cpp | 31 ++++++++++++++++++++++ lib/Target/AMDGPU/SIRegisterInfo.h | 6 +++++ .../Instrumentation/SanitizerCoverage.cpp | 4 ++- .../AArch64/GlobalISel/arm64-instructionselect.mir | 30 +++++++++++++++++++++ test/CodeGen/AArch64/GlobalISel/legalize-mul.mir | 20 ++++++++++++++ test/Instrumentation/SanitizerCoverage/coverage.ll | 14 +++++++++- 11 files changed, 188 insertions(+), 3 deletions(-)