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from 5a211dfa548 [Hexagon] Prevent a stall across zero-latency instructions [...] new 79debc50372 [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions new 7ba710792a7 [AMDGPU][MC][GFX9] Added s_call_b64 new 54a02055fc7 [RISCV] Update MC compression tests

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Summary of changes: lib/Target/AMDGPU/SOPInstructions.td | 12 ++++++++++++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 6 +++++- test/MC/AMDGPU/data.s | 22 +++++++++++----------- test/MC/AMDGPU/sopk.s | 12 ++++++++++++ test/MC/Disassembler/AMDGPU/sopk_gfx9.txt | 9 +++++++++ test/MC/RISCV/cnop.s | 3 ++- test/MC/RISCV/rv32c-only-valid.s | 4 ++-- 7 files changed, 53 insertions(+), 15 deletions(-)