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from ededc9899f1 [InstCombine] fold udiv with common factor from muls with nuw new 7531be0d757 [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

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Summary of changes: lib/Target/AMDGPU/SIRegisterInfo.cpp | 27 +-- test/CodeGen/AMDGPU/spill-offset-calculation.ll | 213 ++++++++++++++++++++++++ 2 files changed, 229 insertions(+), 11 deletions(-) create mode 100644 test/CodeGen/AMDGPU/spill-offset-calculation.ll