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from 0a9f30c50a1 MAINTAINERS: Add myself as riscv port reviewer. new bd93ef7f1a1 RISC-V: Dynamic adjust size of VLA vector according to TARG [...]

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Summary of changes: gcc/config/riscv/riscv-selftests.cc | 10 ++++++ gcc/config/riscv/riscv.cc | 37 +++++++++++++++------- .../{zve64f_zvl128b-1.c => zve32f_zvl1024b-1.c} | 2 +- .../{zve64f_zvl128b-1.c => zve32f_zvl2048b-1.c} | 2 +- .../{zve64f_zvl128b-1.c => zve32f_zvl256b-1.c} | 2 +- .../{zve64f_zvl128b-1.c => zve32f_zvl4096b-1.c} | 2 +- .../{zve64f_zvl128b-1.c => zve32f_zvl512b-1.c} | 2 +- .../autovec/{zve32f-1.c => zve32x_zvl1024b-1.c} | 2 +- .../autovec/{zve32x-1.c => zve32x_zvl2048b-1.c} | 2 +- .../{zve32x_zvl128b-1.c => zve32x_zvl256b-1.c} | 2 +- .../autovec/{zve32x-1.c => zve32x_zvl4096b-1.c} | 2 +- .../{zve32x_zvl128b-1.c => zve32x_zvl512b-1.c} | 2 +- .../riscv/rvv/autovec/zve64d_zvl1024b-1.c | 6 ++++ .../riscv/rvv/autovec/zve64d_zvl2048b-1.c | 6 ++++ .../{zve32x_zvl128b-1.c => zve64d_zvl256b-1.c} | 4 +-- .../riscv/rvv/autovec/zve64d_zvl4096b-1.c | 6 ++++ .../{zve64f_zvl128b-1.c => zve64d_zvl512b-1.c} | 4 +-- .../{zve64d_zvl128b-1.c => zve64f_zvl1024b-1.c} | 2 +- .../{zve64d_zvl128b-1.c => zve64f_zvl2048b-1.c} | 2 +- .../{zve64d_zvl128b-1.c => zve64f_zvl256b-1.c} | 2 +- .../{zve64d_zvl128b-1.c => zve64f_zvl4096b-1.c} | 2 +- .../{zve64d_zvl128b-1.c => zve64f_zvl512b-1.c} | 2 +- .../{zve32f_zvl128b-1.c => zve64x_zvl1024b-1.c} | 2 +- .../autovec/{zve64d-1.c => zve64x_zvl2048b-1.c} | 2 +- .../{zve64x_zvl128b-1.c => zve64x_zvl256b-1.c} | 2 +- .../{zve32f_zvl128b-1.c => zve64x_zvl4096b-1.c} | 2 +- .../{zve64x_zvl128b-1.c => zve64x_zvl512b-1.c} | 2 +- 27 files changed, 77 insertions(+), 36 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve32f_zvl1 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve32f_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve32f_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve32f_zvl4 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve32f_zvl5 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32f-1.c => zve32x_zvl1024b-1.c} (50%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32x-1.c => zve32x_zvl2048b-1.c} (50%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32x_zvl128b-1.c => zve32x_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32x-1.c => zve32x_zvl4096b-1.c} (50%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32x_zvl128b-1.c => zve32x_zvl5 [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl1024b-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl2048b-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32x_zvl128b-1.c => zve64d_zvl2 [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl4096b-1.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64f_zvl128b-1.c => zve64d_zvl5 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d_zvl128b-1.c => zve64f_zvl1 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d_zvl128b-1.c => zve64f_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d_zvl128b-1.c => zve64f_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d_zvl128b-1.c => zve64f_zvl4 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d_zvl128b-1.c => zve64f_zvl5 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32f_zvl128b-1.c => zve64x_zvl1 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64d-1.c => zve64x_zvl2048b-1.c} (50%) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64x_zvl128b-1.c => zve64x_zvl2 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve32f_zvl128b-1.c => zve64x_zvl4 [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{zve64x_zvl128b-1.c => zve64x_zvl5 [...]