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from 7505bb034c7 x86: rework of match_template()'s suffix checking new 6ef35c04dff Fix verilog output when the width is > 1.

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Summary of changes: bfd/ChangeLog | 8 ++++++ bfd/verilog.c | 23 +++++++++++++--- binutils/ChangeLog | 10 +++++++ binutils/objcopy.c | 25 +++++++++++++++-- binutils/testsuite/binutils-all/objcopy.exp | 38 ++++++++++++++++++++++++-- binutils/testsuite/binutils-all/verilog-I4.hex | 6 ++++ 6 files changed, 102 insertions(+), 8 deletions(-) create mode 100644 binutils/testsuite/binutils-all/verilog-I4.hex