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from 9cb56c603f5 [AMDGPU] Fix-up cases where writelane has 2 SGPR operands new 42a92bf21c8 [RISCV] Add MachineInstr immediate verification

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Summary of changes: .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 1 + lib/Target/RISCV/RISCVInstrInfo.cpp | 60 +++++++++++++++++++++- lib/Target/RISCV/RISCVInstrInfo.h | 10 +++- lib/Target/RISCV/RISCVInstrInfo.td | 16 ++++++ lib/Target/RISCV/RISCVSubtarget.cpp | 2 +- lib/Target/RISCV/Utils/RISCVBaseInfo.h | 16 ++++++ test/CodeGen/RISCV/verify-instr.mir | 11 ++++ 7 files changed, 112 insertions(+), 4 deletions(-) create mode 100644 test/CodeGen/RISCV/verify-instr.mir