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from c182f4d14d6 i386: Do not use explicit operands for MOVS instructions [P [...] new 05d75c5bfcf [RISC-V][PR target/119971] Avoid losing shift count masking

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Summary of changes: gcc/config/riscv/bitmanip.md | 59 +++++++++++++------------ gcc/config/riscv/riscv.md | 19 ++------ gcc/testsuite/gcc.target/riscv/pr119971.c | 24 ++++++++++ gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c | 2 +- 4 files changed, 59 insertions(+), 45 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr119971.c