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from 2e5c54d [X86][SSE] Added knownbits through bitcast test new 238ebfa Revert "AMDGPU: Preserve m0 value when spilling" new e2c9a9f Revert "AMDGPU: Remove m0 spilling code" new 2acdc08 Revert "AMDGPU: Make m0 unallocatable" new 47526ba Revert "AMDGPU: Fix not setting kill flag on temp reg when spilling" new dec75f5 Revert "AMDGPU: Fix adding extra implicit def of register" new 2d7b98b Revert "AMDGPU: Fix MMO when splitting spill" new 82bcf46 Revert "AMDGPU: Implement SGPR spilling with scalar stores"

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Summary of changes: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 2 +- lib/Target/AMDGPU/SIISelLowering.cpp | 22 +- lib/Target/AMDGPU/SIInsertWaits.cpp | 43 +--- lib/Target/AMDGPU/SIInstrInfo.cpp | 17 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 275 ++++++--------------- lib/Target/AMDGPU/SIRegisterInfo.h | 11 +- lib/Target/AMDGPU/SIRegisterInfo.td | 8 +- lib/Target/AMDGPU/SIWholeQuadMode.cpp | 2 +- test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll | 36 ++- test/CodeGen/AMDGPU/basic-branch.ll | 2 +- test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 30 +-- test/CodeGen/AMDGPU/detect-dead-lanes.mir | 40 +-- test/CodeGen/AMDGPU/inline-constraints.ll | 5 +- test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll | 3 +- test/CodeGen/AMDGPU/llvm.amdgcn.readlane.ll | 3 +- test/CodeGen/AMDGPU/read_register.ll | 4 +- test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 46 +--- test/CodeGen/AMDGPU/spill-m0.ll | 110 +-------- .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 4 +- .../MIR/AMDGPU/scalar-store-cache-flush.mir | 173 ------------- test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir | 8 +- 21 files changed, 179 insertions(+), 665 deletions(-) delete mode 100644 test/CodeGen/MIR/AMDGPU/scalar-store-cache-flush.mir