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from 3ea47ea1fca RISC-V: Add SiFive extensions, xsfvcp and xsfcease new 63d7d5998e3 RISC-V: Disable misaligned vector access in hook riscv_slow [...]

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Summary of changes: gcc/config/riscv/riscv.cc | 5 ++- gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c | 52 ++++++++++++++++++++++ 2 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c