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from fdda7ea9d5f [CodeGen] Rename DEBUG_TYPE to match passnames new 8f85685860c Enhance synchscope representation

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Summary of changes: docs/LangRef.rst | 80 ++-- include/llvm/Bitcode/LLVMBitCodes.h | 12 +- include/llvm/CodeGen/MachineFunction.h | 2 +- include/llvm/CodeGen/MachineMemOperand.h | 12 +- include/llvm/CodeGen/SelectionDAG.h | 4 +- include/llvm/CodeGen/SelectionDAGNodes.h | 4 +- include/llvm/IR/IRBuilder.h | 12 +- include/llvm/IR/Instructions.h | 204 ++++---- include/llvm/IR/LLVMContext.h | 28 ++ lib/AsmParser/LLLexer.cpp | 2 +- lib/AsmParser/LLParser.cpp | 64 ++- lib/AsmParser/LLParser.h | 3 +- lib/AsmParser/LLToken.h | 2 +- lib/Bitcode/Reader/BitcodeReader.cpp | 92 +++- lib/Bitcode/Writer/BitcodeWriter.cpp | 43 +- lib/CodeGen/AtomicExpandPass.cpp | 8 +- lib/CodeGen/GlobalISel/IRTranslator.cpp | 4 +- lib/CodeGen/MIRParser/MILexer.cpp | 10 + lib/CodeGen/MIRParser/MILexer.h | 3 +- lib/CodeGen/MIRParser/MIParser.cpp | 45 +- lib/CodeGen/MIRPrinter.cpp | 31 +- lib/CodeGen/MachineFunction.cpp | 12 +- lib/CodeGen/MachineInstr.cpp | 6 +- lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 +- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 18 +- lib/IR/AsmWriter.cpp | 66 ++- lib/IR/Core.cpp | 21 +- lib/IR/Instruction.cpp | 11 +- lib/IR/Instructions.cpp | 68 +-- lib/IR/LLVMContext.cpp | 18 + lib/IR/LLVMContextImpl.cpp | 14 + lib/IR/LLVMContextImpl.h | 14 + lib/IR/Verifier.cpp | 4 +- lib/Target/ARM/ARMISelLowering.cpp | 6 +- lib/Target/SystemZ/SystemZISelLowering.cpp | 4 +- lib/Target/X86/X86ISelLowering.cpp | 10 +- lib/Transforms/IPO/GlobalOpt.cpp | 10 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 10 +- lib/Transforms/Instrumentation/ThreadSanitizer.cpp | 7 +- lib/Transforms/Scalar/GVN.cpp | 2 +- lib/Transforms/Scalar/JumpThreading.cpp | 2 +- lib/Transforms/Scalar/SROA.cpp | 6 +- lib/Transforms/Utils/FunctionComparator.cpp | 18 +- test/Assembler/atomic.ll | 26 +- test/Bitcode/atomic-no-syncscope.ll | 17 + test/Bitcode/atomic-no-syncscope.ll.bc | Bin 0 -> 1000 bytes test/Bitcode/atomic.ll | 4 +- test/Bitcode/compatibility-3.6.ll | 24 +- test/Bitcode/compatibility-3.7.ll | 24 +- test/Bitcode/compatibility-3.8.ll | 24 +- test/Bitcode/compatibility-3.9.ll | 24 +- test/Bitcode/compatibility-4.0.ll | 24 +- test/Bitcode/compatibility.ll | 24 +- test/Bitcode/memInstructions.3.2.ll | 104 ++-- .../AArch64/GlobalISel/arm64-irtranslator.ll | 8 +- test/CodeGen/AArch64/fence-singlethread.ll | 2 +- test/CodeGen/AMDGPU/syncscopes.ll | 19 + test/CodeGen/ARM/fence-singlethread.ll | 2 +- test/CodeGen/MIR/AArch64/atomic-memoperands.mir | 4 +- test/CodeGen/MIR/AMDGPU/syncscopes.mir | 98 ++++ test/CodeGen/PowerPC/atomics-regression.ll | 528 ++++++++++----------- test/Instrumentation/ThreadSanitizer/atomic.ll | 8 +- test/Linker/Inputs/syncscope-1.ll | 6 + test/Linker/Inputs/syncscope-2.ll | 6 + test/Linker/syncscopes.ll | 11 + test/Transforms/GVN/PRE/atomic.ll | 6 +- test/Transforms/InstCombine/consecutive-fences.ll | 12 +- test/Transforms/Sink/fence.ll | 8 +- unittests/Analysis/AliasAnalysisTest.cpp | 5 +- 69 files changed, 1227 insertions(+), 791 deletions(-) create mode 100644 test/Bitcode/atomic-no-syncscope.ll create mode 100644 test/Bitcode/atomic-no-syncscope.ll.bc create mode 100644 test/CodeGen/AMDGPU/syncscopes.ll create mode 100644 test/CodeGen/MIR/AMDGPU/syncscopes.mir create mode 100644 test/Linker/Inputs/syncscope-1.ll create mode 100644 test/Linker/Inputs/syncscope-2.ll create mode 100644 test/Linker/syncscopes.ll