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from fcbb8456a58 RISC-V: Add new constraint R for register even-odd pairs new 423ee61fdd9 testsuite: arm: Add -mtune to all arm_cpu_* effective targets new 5601c411f4f [PATCH v2 1/2] RISC-V: Document thead-c906, xiangshan-nanhu [...] new 4aa01ecc5c1 [PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture new f111d8e20b6 testsuite: arm: Mark pr81812.C as xfail for thumb1

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Summary of changes: gcc/config/riscv/riscv-cores.def | 8 +++ gcc/config/riscv/riscv.cc | 22 +++++++ gcc/doc/invoke.texi | 12 ++-- gcc/testsuite/g++.dg/torture/pr81812.C | 2 + .../gcc.target/riscv/mcpu-tt-ascalon-d8.c | 76 ++++++++++++++++++++++ gcc/testsuite/lib/target-supports.exp | 27 ++++---- 6 files changed, 130 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-tt-ascalon-d8.c