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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/qemu.

from 45240eed4f Merge remote-tracking branch 'remotes/armbru/tags/pull-yank- [...] adds 5d9d376979 mac_oldworld: remove duplicate bus check for PPC_INPUT(env) adds 49ac51ae80 mac_oldworld: move initialisation of grackle before heathrow adds 370022ce31 macio: move heathrow PIC inside macio-oldworld device adds 6ce97b225e mac_newworld: delay wiring of PCI IRQs in New World machine adds 7e4d62dfee macio: move OpenPIC inside macio-newworld device adds b73eb72792 macio: wire macio GPIOs to OpenPIC using sysbus IRQs adds 7b3180f911 macio: don't set user_creatable to false adds c0dd6654f2 Merge remote-tracking branch 'remotes/mcayland/tags/qemu-mac [...] adds 0a6a8bc8eb tcg: Use tcg_out_dupi_vec from temp_load adds 4e18617555 tcg: Increase tcg_out_dupi_vec immediate to int64_t adds ee17db83d2 tcg: Consolidate 3 bits into enum TCGTempKind adds e01fa97dea tcg: Add temp_readonly adds bdb38b95f7 tcg: Expand TCGTemp.val to 64-bits adds 6fcb98eda1 tcg: Rename struct tcg_temp_info to TempOptInfo adds 54795544e4 tcg: Expand TempOptInfo to 64-bits adds c0522136ad tcg: Introduce TYPE_CONST temporaries adds 4c868ce645 tcg/optimize: Improve find_better_copy adds 8f17a975e6 tcg/optimize: Adjust TempOptInfo allocation adds 8fe35e0444 tcg/optimize: Use tcg_constant_internal with constant folding adds 0b4286dd15 tcg: Convert tcg_gen_dupi_vec to TCG_CONST adds 0e1ea43a9d tcg: Use tcg_constant_i32 with icount expander adds 11d11d61bd tcg: Use tcg_constant_{i32,i64} with tcg int expanders adds 80c44bba42 tcg: Use tcg_constant_{i32,i64} with tcg plugins adds 88d4005b09 tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders adds 1bd1af98d7 tcg/tci: Add special tci_movi_{i32,i64} opcodes adds c58f4c97b2 tcg: Remove movi and dupi opcodes adds efe86b21ea tcg: Add tcg_reg_alloc_dup2 adds 9739a052ad tcg/i386: Use tcg_constant_vec with tcg vec expanders adds be986adb35 tcg: Remove tcg_gen_dup{8,16,32,64}i_vec adds 44aa59a099 tcg/ppc: Use tcg_constant_vec with tcg vec expanders adds 10061ffe56 tcg/aarch64: Use tcg_constant_vec with tcg vec expanders adds 4cacecaaa2 decodetree: Open files with encoding='utf-8' adds 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] new 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA new b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions new 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 new 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment new bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition new 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 new b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() new ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() new 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 new f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] new 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] new d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] new 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] new bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 new 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 new bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 new 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 new 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 new 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() new 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' new f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif new 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs new e9927723ba target/mips: Move common helpers from helper.c to cpu.c new 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c new ca2690e36a target/mips: Fix code style for checkpatch.pl new f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c new 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c new e31309365e target/mips/translate: Extract DisasContext structure new 46c9e2b3dd target/mips/translate: Add declarations for generic code new 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] new 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] new 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] new 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h new 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set new 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] new d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode new 25a1362875 target/mips: Introduce ase_msa_available() helper new 72f31f60f8 target/mips: Simplify msa_reset() new aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA new 33942f9460 target/mips: Simplify MSA TCG logic new 7e2a619a04 target/mips: Remove now unused ASE_MSA definition new e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers new 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() new 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods new 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() new 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c new 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c new edb2384728 target/mips: Extract MSA helper definitions new 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' new 80e64a380f target/mips: Extract MSA translation routines new 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() new c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE new 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree new a685f7d075 target/mips: Extract LSA/DLSA translation generators new 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes new 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] new 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code new aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree new ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree new 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree new 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree new dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree new 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree new 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree new 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree new 6648042afb target/mips: Remove CPU_R5900 definition new fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition new eaca85763b target/mips: Remove vendor specific CPU definitions new cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias new 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...]

The 70 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: accel/tcg/plugin-gen.c | 49 +- docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - hw/misc/macio/gpio.c | 24 +- hw/misc/macio/macio.c | 53 +- hw/ppc/mac_newworld.c | 71 +- hw/ppc/mac_oldworld.c | 76 +- include/exec/gen-icount.h | 25 +- include/hw/misc/macio/gpio.h | 2 - include/hw/misc/macio/macio.h | 4 +- include/tcg/tcg-op.h | 17 +- include/tcg/tcg-opc.h | 11 +- include/tcg/tcg.h | 50 +- linux-user/mips/cpu_loop.c | 7 +- scripts/decodetree.py | 9 +- target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + tcg/aarch64/tcg-target.c.inc | 32 +- tcg/arm/tcg-target.c.inc | 1 - tcg/i386/tcg-target.c.inc | 112 +- tcg/mips/tcg-target.c.inc | 2 - tcg/optimize.c | 249 +- tcg/ppc/tcg-target.c.inc | 90 +- tcg/riscv/tcg-target.c.inc | 2 - tcg/s390/tcg-target.c.inc | 2 - tcg/sparc/tcg-target.c.inc | 2 - tcg/tcg-op-gvec.c | 127 +- tcg/tcg-op-vec.c | 52 +- tcg/tcg-op.c | 227 +- tcg/tcg.c | 488 ++- tcg/tci.c | 4 +- tcg/tci/tcg-target.c.inc | 6 +- 60 files changed, 5837 insertions(+), 5314 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c