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from 72319171e1b Daily bump. new 7c190f93cd5 RISC-V: Support scheduling for sifive p400 series new 91e09b3a7e9 RISC-V: Add sifive-p450, sifive-p67 to -mcpu

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Summary of changes: gcc/config/riscv/riscv-cores.def | 10 ++ gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 17 +++ gcc/config/riscv/riscv.h | 1 + gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/sifive-p400.md | 174 ++++++++++++++++++++++ gcc/doc/invoke.texi | 7 +- gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c | 34 +++++ gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c | 40 +++++ 9 files changed, 283 insertions(+), 4 deletions(-) create mode 100644 gcc/config/riscv/sifive-p400.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c