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from d6987046197 [SLP] add test with prefer-vector-width function attribute; [...] new cf65f7210c0 Revert "[LoopVectorize][PowerPC] Estimate int and float reg [...] new 53208ba3c03 AMDGPU: Fix i16 arithmetic pattern redundancy

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Summary of changes: include/llvm/Analysis/TargetTransformInfo.h | 35 +-- include/llvm/Analysis/TargetTransformInfoImpl.h | 15 +- include/llvm/CodeGen/BasicTTIImpl.h | 2 + lib/Analysis/TargetTransformInfo.cpp | 12 +- lib/Target/AArch64/AArch64TargetTransformInfo.h | 3 +- lib/Target/AMDGPU/VOP2Instructions.td | 101 ++----- lib/Target/ARM/ARMTargetTransformInfo.h | 3 +- lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 35 +-- lib/Target/PowerPC/PPCTargetTransformInfo.h | 8 +- lib/Target/SystemZ/SystemZTargetTransformInfo.cpp | 3 +- lib/Target/SystemZ/SystemZTargetTransformInfo.h | 2 +- .../WebAssembly/WebAssemblyTargetTransformInfo.cpp | 5 +- .../WebAssembly/WebAssemblyTargetTransformInfo.h | 2 +- lib/Target/X86/X86TargetTransformInfo.cpp | 3 +- lib/Target/X86/X86TargetTransformInfo.h | 2 +- lib/Target/XCore/XCoreTargetTransformInfo.h | 3 +- lib/Transforms/Scalar/LoopStrengthReduce.cpp | 4 +- lib/Transforms/Vectorize/LoopVectorize.cpp | 153 ++++------- lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +- .../AMDGPU/GlobalISel/inst-select-ashr.s16.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-lshr.s16.mir | 16 +- .../AMDGPU/GlobalISel/inst-select-shl.s16.mir | 16 +- test/CodeGen/AMDGPU/idot2.ll | 9 +- test/CodeGen/AMDGPU/idot4s.ll | 17 +- test/CodeGen/AMDGPU/idot4u.ll | 90 +++---- test/CodeGen/AMDGPU/idot8s.ll | 300 +++++++++------------ test/CodeGen/AMDGPU/idot8u.ll | 63 +++-- test/CodeGen/AMDGPU/preserve-hi16.ll | 154 +++++++++-- test/CodeGen/AMDGPU/sdwa-peephole.ll | 15 +- test/Transforms/LoopVectorize/PowerPC/reg-usage.ll | 179 ------------ .../LoopVectorize/X86/reg-usage-debug.ll | 12 +- test/Transforms/LoopVectorize/X86/reg-usage.ll | 34 +-- 32 files changed, 476 insertions(+), 838 deletions(-) delete mode 100644 test/Transforms/LoopVectorize/PowerPC/reg-usage.ll