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from 15e55f3fb55 Daily bump. new 7cf7149ec83 Match:Support IMM=-1 for signed scalar SAT_ADD IMM form1 new 4962e6d0810 RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1. new 70fdc02b609 Match:Support signed vector SAT_ADD IMM form 1 new a91679a3d9f RISC-V: Add testcases for signed vector SAT_ADD IMM form 1

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Summary of changes: gcc/match.pd | 29 ++- .../riscv/rvv/autovec/sat/vec_sat_arith.h | 25 +++ .../riscv/rvv/autovec/sat/vec_sat_data.h | 240 +++++++++++++++++++++ ...sat_s_add-1-s64.c => vec_sat_s_add_imm-1-i16.c} | 4 +- ...sat_s_add-1-s16.c => vec_sat_s_add_imm-1-i32.c} | 4 +- ...sat_s_add-1-s64.c => vec_sat_s_add_imm-1-i64.c} | 4 +- ..._sat_s_add-1-s64.c => vec_sat_s_add_imm-1-i8.c} | 4 +- .../rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c | 28 +++ .../rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c | 28 +++ .../rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c | 28 +++ .../rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c | 28 +++ .../sat/vec_sat_s_add_imm_type_check-1-i16.c | 9 + .../sat/vec_sat_s_add_imm_type_check-1-i32.c | 9 + ...1-u32.c => vec_sat_s_add_imm_type_check-1-i8.c} | 5 +- .../{sat_s_add_imm-2.c => sat_s_add_imm-1-i16.c} | 27 ++- .../{sat_s_add_imm-3.c => sat_s_add_imm-1-i32.c} | 26 ++- .../{sat_s_add_imm-4.c => sat_s_add_imm-1-i64.c} | 22 +- .../{sat_s_add_imm-1.c => sat_s_add_imm-1-i8.c} | 22 +- ...s_add_imm-run-2.c => sat_s_add_imm-run-1-i16.c} | 6 + ...s_add_imm-run-3.c => sat_s_add_imm-run-1-i32.c} | 6 + ...s_add_imm-run-4.c => sat_s_add_imm-run-1-i64.c} | 6 + ..._s_add_imm-run-1.c => sat_s_add_imm-run-1-i8.c} | 6 + ..._imm-2-1.c => sat_s_add_imm_type_check-1-i16.c} | 0 ..._imm-3-1.c => sat_s_add_imm_type_check-1-i32.c} | 0 ...d_imm-1-1.c => sat_s_add_imm_type_check-1-i8.c} | 0 gcc/tree-ssa-math-opts.cc | 30 ++- 26 files changed, 576 insertions(+), 20 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_s_add-1-s64.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_s_add-1-s16.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_s_add-1-s64.c => vec_ [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_s_add-1-s64.c => vec_ [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_im [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/{vec_sat_u_add_imm_reconcile-1 [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-2.c => sat_s_add_imm-1-i1 [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-3.c => sat_s_add_imm-1-i3 [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-4.c => sat_s_add_imm-1-i6 [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-1.c => sat_s_add_imm-1-i8 [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-run-2.c => sat_s_add_imm- [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-run-3.c => sat_s_add_imm- [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-run-4.c => sat_s_add_imm- [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-run-1.c => sat_s_add_imm- [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-2-1.c => sat_s_add_imm_ty [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-3-1.c => sat_s_add_imm_ty [...] rename gcc/testsuite/gcc.target/riscv/sat/{sat_s_add_imm-1-1.c => sat_s_add_imm_ty [...]