This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository gcc.
from 01fe115ba7e libgomp.c/target-51.c: Accept more error-msg variants in dg-output new c3e720887ec RISC-V: Add (u)int8_t to binop tests. new 51795b91073 RISC-V: Implement vec_set and vec_extract. new 9b24611acf2 RISC-V: Add sign-extending variants for vmv.x.s. new 47ffabaf669 RISC-V: Add autovec FP binary operations. new da6cc50819c RISC-V: Add autovec FP unary operations.
The 5 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: gcc/config/riscv/autovec-opt.md | 29 +++ gcc/config/riscv/autovec.md | 151 ++++++++++++- gcc/config/riscv/riscv-protos.h | 12 +- gcc/config/riscv/riscv-v.cc | 103 ++++++++- gcc/config/riscv/riscv.cc | 27 ++- gcc/config/riscv/vector-iterators.md | 33 +++ .../gcc.target/riscv/rvv/autovec/binop/shift-run.c | 4 + .../riscv/rvv/autovec/binop/shift-rv32gcv.c | 10 +- .../riscv/rvv/autovec/binop/shift-rv64gcv.c | 6 +- .../riscv/rvv/autovec/binop/shift-template.h | 5 +- .../gcc.target/riscv/rvv/autovec/binop/vadd-run.c | 18 +- .../riscv/rvv/autovec/binop/vadd-rv32gcv.c | 7 +- .../riscv/rvv/autovec/binop/vadd-rv64gcv.c | 7 +- .../riscv/rvv/autovec/binop/vadd-template.h | 18 +- .../autovec/binop/{vadd-run.c => vadd-zvfh-run.c} | 23 +- .../gcc.target/riscv/rvv/autovec/binop/vand-run.c | 6 + .../riscv/rvv/autovec/binop/vand-rv32gcv.c | 4 +- .../riscv/rvv/autovec/binop/vand-rv64gcv.c | 4 +- .../riscv/rvv/autovec/binop/vand-template.h | 7 +- .../gcc.target/riscv/rvv/autovec/binop/vdiv-run.c | 12 +- .../riscv/rvv/autovec/binop/vdiv-rv32gcv.c | 13 +- .../riscv/rvv/autovec/binop/vdiv-rv64gcv.c | 13 +- .../riscv/rvv/autovec/binop/vdiv-template.h | 12 +- .../autovec/binop/{vdiv-run.c => vdiv-zvfh-run.c} | 18 +- .../gcc.target/riscv/rvv/autovec/binop/vmax-run.c | 13 +- .../riscv/rvv/autovec/binop/vmax-rv32gcv.c | 7 +- .../riscv/rvv/autovec/binop/vmax-rv64gcv.c | 7 +- .../riscv/rvv/autovec/binop/vmax-template.h | 13 +- .../autovec/binop/{vmax-run.c => vmax-zvfh-run.c} | 19 +- .../gcc.target/riscv/rvv/autovec/binop/vmin-run.c | 14 +- .../riscv/rvv/autovec/binop/vmin-rv32gcv.c | 7 +- .../riscv/rvv/autovec/binop/vmin-rv64gcv.c | 7 +- .../riscv/rvv/autovec/binop/vmin-template.h | 13 +- .../autovec/binop/{vmin-run.c => vmin-zvfh-run.c} | 18 +- .../gcc.target/riscv/rvv/autovec/binop/vmul-run.c | 16 +- .../riscv/rvv/autovec/binop/vmul-rv32gcv.c | 4 +- .../riscv/rvv/autovec/binop/vmul-rv64gcv.c | 4 +- .../riscv/rvv/autovec/binop/vmul-template.h | 17 +- .../autovec/binop/{vmul-run.c => vmul-zvfh-run.c} | 18 +- .../gcc.target/riscv/rvv/autovec/binop/vor-run.c | 6 + .../riscv/rvv/autovec/binop/vor-rv32gcv.c | 4 +- .../riscv/rvv/autovec/binop/vor-rv64gcv.c | 4 +- .../riscv/rvv/autovec/binop/vor-template.h | 7 +- .../gcc.target/riscv/rvv/autovec/binop/vrem-run.c | 4 + .../riscv/rvv/autovec/binop/vrem-rv32gcv.c | 9 +- .../riscv/rvv/autovec/binop/vrem-rv64gcv.c | 6 +- .../riscv/rvv/autovec/binop/vrem-template.h | 5 +- .../gcc.target/riscv/rvv/autovec/binop/vsub-run.c | 28 ++- .../riscv/rvv/autovec/binop/vsub-rv32gcv.c | 12 +- .../riscv/rvv/autovec/binop/vsub-rv64gcv.c | 12 +- .../riscv/rvv/autovec/binop/vsub-template.h | 26 ++- .../autovec/binop/{vsub-run.c => vsub-zvfh-run.c} | 32 +-- .../gcc.target/riscv/rvv/autovec/binop/vxor-run.c | 6 + .../riscv/rvv/autovec/binop/vxor-rv32gcv.c | 4 +- .../riscv/rvv/autovec/binop/vxor-rv64gcv.c | 4 +- .../riscv/rvv/autovec/binop/vxor-template.h | 7 +- .../gcc.target/riscv/rvv/autovec/unop/abs-run.c | 46 ++-- .../riscv/rvv/autovec/unop/abs-rv32gcv.c | 3 +- .../riscv/rvv/autovec/unop/abs-rv64gcv.c | 3 +- .../riscv/rvv/autovec/unop/abs-template.h | 17 +- .../riscv/rvv/autovec/unop/abs-zvfh-run.c | 35 +++ .../gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c | 30 +++ .../riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c | 12 ++ .../riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c | 12 ++ .../riscv/rvv/autovec/unop/vfsqrt-template.h | 31 +++ .../riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c | 33 +++ .../gcc.target/riscv/rvv/autovec/unop/vneg-run.c | 8 +- .../riscv/rvv/autovec/unop/vneg-rv32gcv.c | 3 +- .../riscv/rvv/autovec/unop/vneg-rv64gcv.c | 3 +- .../riscv/rvv/autovec/unop/vneg-template.h | 5 +- .../autovec/unop/{vneg-run.c => vneg-zvfh-run.c} | 11 +- .../riscv/rvv/autovec/vls-vlmax/vec_extract-1.c | 59 +++++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-2.c | 70 ++++++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-3.c | 71 ++++++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-4.c | 74 +++++++ .../riscv/rvv/autovec/vls-vlmax/vec_extract-run.c | 239 ++++++++++++++++++++ .../rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c | 77 +++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-1.c | 62 ++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-2.c | 74 +++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-3.c | 76 +++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-4.c | 79 +++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-run.c | 240 +++++++++++++++++++++ .../riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c | 78 +++++++ .../gcc.target/riscv/rvv/autovec/zvfhmin-1.c | 16 +- gcc/testsuite/lib/target-supports.exp | 49 +++++ 85 files changed, 2148 insertions(+), 263 deletions(-) copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vadd-run.c => vadd-zvfh-run [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vdiv-run.c => vdiv-zvfh-run [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vmax-run.c => vmax-zvfh-run [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vmin-run.c => vmin-zvfh-run [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vmul-run.c => vmul-zvfh-run [...] copy gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/{vsub-run.c => vsub-zvfh-run [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c copy gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/{vneg-run.c => vneg-zvfh-run. [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extrac [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zv [...]
-
git＠git.linaro.org