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from d87ee7f1c9c Clean up loop-closed PHIs after loop finalize new 6a5bb4705fb RISC-V: Handle implied extension in canonical ordering. new b03be74bad0 RISC-V: Support zicsr and zifencei extension for -march. new 4b81528241c RISC-V: Support version controling for ISA standard extensions

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Summary of changes: gcc/common/config/riscv/riscv-common.c | 458 ++++++++++++++++++++++---- gcc/config.gcc | 17 +- gcc/config.in | 12 + gcc/config/riscv/riscv-opts.h | 16 + gcc/config/riscv/riscv.h | 9 +- gcc/config/riscv/riscv.md | 5 +- gcc/config/riscv/riscv.opt | 20 ++ gcc/configure | 62 ++++ gcc/configure.ac | 10 + gcc/testsuite/gcc.target/riscv/arch-10.c | 6 + gcc/testsuite/gcc.target/riscv/arch-11.c | 5 + gcc/testsuite/gcc.target/riscv/arch-8.c | 5 + gcc/testsuite/gcc.target/riscv/arch-9.c | 6 + gcc/testsuite/gcc.target/riscv/attribute-11.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-12.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-13.c | 2 +- gcc/testsuite/gcc.target/riscv/attribute-14.c | 6 + gcc/testsuite/gcc.target/riscv/attribute-15.c | 6 + gcc/testsuite/gcc.target/riscv/attribute-16.c | 6 + gcc/testsuite/gcc.target/riscv/attribute-17.c | 6 + gcc/testsuite/gcc.target/riscv/attribute-6.c | 6 - gcc/testsuite/gcc.target/riscv/attribute-8.c | 4 +- gcc/testsuite/gcc.target/riscv/attribute-9.c | 2 +- 23 files changed, 586 insertions(+), 87 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/arch-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-17.c delete mode 100644 gcc/testsuite/gcc.target/riscv/attribute-6.c