This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-monorepo.

from 73e71c39503 [WebAssembly] Fix comments in ExplicitLocals (NFC) adds 4b841979c47 Drop SE cache early because loop parent can change in LoopS [...] adds e9853a02625 [SymbolContext] Rewrite operator== to be more concise. adds 633a67e5b7d [CompilerType] Remove dead code. NFCI. adds a850e77d8e7 [CompilerType] Simplify operator!=. NFCI. adds 4e1bfe7ac35 [RegisterValue] Rewrite operator!= in terms of operator==. NFCI. adds bf2ff622a31 [X86] Add test case from PR38217. NFC adds 2a75f0eac9f [mips] Show a regular error message on attempt to use one b [...] adds aef0837de80 [mips] Show an error on attempt to use 64-bit PC-relative r [...] adds e5a8bcc96b8 [PowerPC] Fix CR Bit spill pseudo expansion adds fc0ae46fee4 [InstCombine] [NFC] update testcases for canonicalize MUL w [...] adds d57abdac186 [PowerPC] Complete the custom legalization of vector int to [...] adds 645d02b4846 [PowerPC][NFC] Macro for register set defs for the Asm Parser adds 30ffad93013 [CodeGen] Replace '@' characters in block descriptors' symb [...] adds 8cac4ec796c [X86] Add custom type legalization for SIGN_EXTEND_VECTOR_I [...] new 72c2927e891 [X86] Don't mark SEXTLOAD from v4i8/v4i16/v8i8 as Custom on [...]

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang/lib/CodeGen/CGBlocks.cpp | 3 + clang/test/CodeGenObjC/block-desc-str.m | 14 + clang/test/CodeGenObjCXX/block-nested-in-lambda.mm | 4 +- lldb/source/Symbol/CompilerType.cpp | 13 +- lldb/source/Symbol/SymbolContext.cpp | 7 +- lldb/source/Utility/RegisterValue.cpp | 27 +- .../Mips/MCTargetDesc/MipsELFObjectWriter.cpp | 9 +- llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 165 +- .../PowerPC/Disassembler/PPCDisassembler.cpp | 209 +-- .../Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 60 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 59 +- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 79 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 13 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 55 +- llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp | 10 +- .../PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir | 121 ++ .../CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll | 1314 +++------------ .../CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll | 311 ++-- .../CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll | 884 ++++------ .../CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll | 1415 ++++------------ .../CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll | 1707 +++++++------------- llvm/test/CodeGen/PowerPC/vsx.ll | 34 +- llvm/test/CodeGen/X86/madd.ll | 94 +- llvm/test/CodeGen/X86/pmovsx-inreg.ll | 18 +- llvm/test/CodeGen/X86/pmul.ll | 106 +- llvm/test/CodeGen/X86/pr38217.ll | 79 + llvm/test/CodeGen/X86/vec_cast.ll | 7 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 27 +- llvm/test/CodeGen/X86/vector-sext.ll | 696 +++----- llvm/test/CodeGen/X86/vsel-cmp-load.ll | 14 +- llvm/test/MC/Mips/unsupported-relocation.s | 10 +- llvm/test/Transforms/InstCombine/mul.ll | 25 +- 32 files changed, 2495 insertions(+), 5094 deletions(-) create mode 100644 clang/test/CodeGenObjC/block-desc-str.m create mode 100644 llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir create mode 100644 llvm/test/CodeGen/X86/pr38217.ll