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from b575f37a342 ARM: Fix conditional execution [PR113915] new 9ae83078fe4 RISC-V: Adjust vec unit-stride load/store costs. new 59554a50be8 RISC-V: Use vmv1r.v instead of vmv.v.v for fma output reloa [...]

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Summary of changes: gcc/config/riscv/riscv-vector-costs.cc | 86 ++++++++++++++++--- gcc/config/riscv/riscv-vector-costs.h | 10 +++ gcc/config/riscv/vector.md | 96 +++++++++++----------- .../gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c | 51 ++++++++++++ .../gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c | 51 ++++++++++++ .../gcc.target/riscv/rvv/autovec/pr114200.c | 18 ++++ .../gcc.target/riscv/rvv/autovec/pr114202.c | 20 +++++ 7 files changed, 274 insertions(+), 58 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-1.c create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/vse-slp-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114200.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114202.c