This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master in repository llvm.
from 9590c4473fd [X86] Add test case for trunc_packus_v16i32_v16i8 with avx5 [...] new 45cd9c275c7 AMDGPU: Use SGPR_128 instead of SReg_128 for vregs
The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.
Summary of changes: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 4 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 4 +- lib/Target/AMDGPU/SIISelLowering.cpp | 12 ++-- lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 2 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 15 +++-- lib/Target/AMDGPU/SIRegisterInfo.td | 1 + .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 2 +- .../GlobalISel/inst-select-concat-vectors.mir | 32 +++++----- .../AMDGPU/GlobalISel/inst-select-insert.mir | 14 ++-- .../GlobalISel/inst-select-load-constant.mir | 40 ++++++------ .../AMDGPU/GlobalISel/inst-select-merge-values.mir | 8 +-- .../AMDGPU/GlobalISel/inst-select-trunc.mir | 4 +- .../GlobalISel/inst-select-unmerge-values.mir | 4 +- .../llvm.amdgcn.raw.buffer.store.format.f16.ll | 44 ++++++------- .../llvm.amdgcn.raw.buffer.store.format.f32.ll | 24 +++---- .../GlobalISel/llvm.amdgcn.raw.buffer.store.ll | 66 +++++++++---------- .../AMDGPU/buffer-intrinsics-mmo-offsets.ll | 2 +- .../AMDGPU/coalescer-extend-pruned-subrange.mir | 20 +++--- .../AMDGPU/coalescer-identical-values-undef.mir | 14 ++-- ...coalescer-subranges-another-copymi-not-live.mir | 20 +++--- .../coalescer-subranges-another-prune-error.mir | 16 ++--- test/CodeGen/AMDGPU/coalescer-subreg-join.mir | 4 +- .../AMDGPU/coalescer-subregjoin-fullcopy.mir | 6 +- .../coalescer-with-subregs-bad-identical.mir | 14 ++-- test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 8 +-- test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir | 22 +++---- test/CodeGen/AMDGPU/dce-disjoint-intervals.mir | 14 ++-- test/CodeGen/AMDGPU/detect-dead-lanes.mir | 74 +++++++++++----------- test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 4 +- test/CodeGen/AMDGPU/fold-imm-copy.mir | 2 +- test/CodeGen/AMDGPU/fold-imm-f16-f32.mir | 18 +++--- test/CodeGen/AMDGPU/fold-multiple.mir | 2 +- test/CodeGen/AMDGPU/global-load-store-atomics.mir | 2 +- test/CodeGen/AMDGPU/memory_clause.mir | 18 +++--- test/CodeGen/AMDGPU/merge-load-store.mir | 4 +- test/CodeGen/AMDGPU/mubuf-legalize-operands.mir | 30 ++++----- .../AMDGPU/optimize-negated-cond-exec-masking.mir | 8 +-- test/CodeGen/AMDGPU/phi-elimination-end-cf.mir | 2 +- test/CodeGen/AMDGPU/promote-constOffset-to-imm.mir | 8 +-- test/CodeGen/AMDGPU/regbank-reassign.mir | 2 +- test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir | 24 +++---- test/CodeGen/AMDGPU/regcoal-subrange-join.mir | 6 +- ...coalescing-remove-partial-redundancy-assert.mir | 6 +- test/CodeGen/AMDGPU/rename-independent-subregs.mir | 6 +- test/CodeGen/AMDGPU/schedule-regpressure.mir | 2 +- test/CodeGen/AMDGPU/spill-before-exec.mir | 44 ++++++------- test/CodeGen/AMDGPU/splitkit.mir | 10 +-- test/CodeGen/AMDGPU/subreg-split-live-in-error.mir | 6 +- test/CodeGen/AMDGPU/subreg_interference.mir | 4 +- test/CodeGen/AMDGPU/subvector-test.mir | 2 +- 52 files changed, 356 insertions(+), 352 deletions(-)