This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O1 in repository toolchain/ci/gcc.

from 4fb1ee669cc c++: overload sets and placeholder return type [PR64194] adds bc7d2977d10 Fix PR ada/98230 adds 00b3e8408ab arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics adds e875b07405f arm: Add vst1_lane_bf16 + vstq_lane_bf16 intrinsics adds caee9e676a5 arm: Add vld1_bf16 + vld1q_bf16 intrinsics adds f09b8cc616a arm: Add vst1_bf16 + vst1q_bf16 intrinsics adds 69191da4f4f arm: Add vldN_lane_bf16 + vldNq_lane_bf16 intrisics adds 00be3a70dd8 arm: Add vstN_lane_bf16 + vstNq_lane_bf16 intrisics adds 702e45ee471 aarch64: intrinsics to convert BFloat16 to Float32 adds c25f7eac655 aarch64: intrinsics to extract half of bf16 vector adds 907525c3063 Daily bump. adds 1c92fb9ec1e Daily bump.

No new revisions were added by this update.

Summary of changes: gcc/ChangeLog | 71 +++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 6 + gcc/ada/exp_attr.adb | 6 +- gcc/config/aarch64/aarch64-simd-builtins.def | 9 ++ gcc/config/aarch64/aarch64-simd.md | 49 ++++++ gcc/config/aarch64/arm_bf16.h | 7 + gcc/config/aarch64/arm_neon.h | 35 +++++ gcc/config/arm/arm-builtins.c | 3 + gcc/config/arm/arm_neon.h | 166 +++++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 42 +++--- gcc/config/arm/iterators.md | 2 +- gcc/cp/ChangeLog | 10 ++ gcc/testsuite/ChangeLog | 80 ++++++++++ .../aarch64/advsimd-intrinsics/bf16_get.c | 27 ++++ .../aarch64/advsimd-intrinsics/bfcvt-compile.c | 40 +++++ .../advsimd-intrinsics/vld2_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vld2q_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vld3_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vld3q_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vld4_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vld4q_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst2_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst2q_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst3_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst3q_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst4_lane_bf16_indices_1.c | 2 +- .../advsimd-intrinsics/vst4q_lane_bf16_indices_1.c | 2 +- gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c | 29 ++++ .../gcc.target/arm/simd/vld1_lane_bf16_1.c | 22 +++ .../gcc.target/arm/simd/vld1_lane_bf16_indices_1.c | 19 +++ .../arm/simd/vld1q_lane_bf16_indices_1.c | 19 +++ .../gcc.target/arm/simd/vldn_lane_bf16_1.c | 79 ++++++++++ gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c | 29 ++++ .../gcc.target/arm/simd/vst1_lane_bf16_1.c | 22 +++ .../gcc.target/arm/simd/vst1_lane_bf16_indices_1.c | 17 +++ .../gcc.target/arm/simd/vstn_lane_bf16_1.c | 73 +++++++++ .../arm/simd/vstq1_lane_bf16_indices_1.c | 17 +++ gcc/testsuite/gnat.dg/modular6.adb | 15 ++ 39 files changed, 884 insertions(+), 36 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bf16_get.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vldn_lane_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1_lane_bf16_indices_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vstn_lane_bf16_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vstq1_lane_bf16_indices_1.c create mode 100644 gcc/testsuite/gnat.dg/modular6.adb