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from e07a876c076 tree-optimization/105946 - avoid accessing excess args from [...] new 4bf0dcb0492 RISC-V: add consecutive_bits_operand predicate new 0247ad3e0f4 RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w

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Summary of changes: gcc/config/riscv/bitmanip.md | 44 ++++++++++++++++++++++++++++++ gcc/config/riscv/predicates.md | 11 ++++++++ gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++++ 3 files changed, 68 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c