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from a9ae16db8cb i386:Add missing OPTION_MASK_ISA_AVX512VL in i386-builtin.d [...] new 8351535f20b riscv: Add basic XThead* vendor extension support new c36fb3ca9ee riscv: riscv-cores.def: Add T-Head XuanTie C906 new b77c32273b4 riscv: thead: Add support for the XTheadBa ISA extension new d328d3a6f87 riscv: thead: Add support for the XTheadBs ISA extension new c493fa38924 riscv: thead: Add support for the XTheadBb ISA extension new 8e7ffe126de riscv: thead: Add support for the XTheadCondMov ISA extensions new b2a1bef96da riscv: thead: Add support for the XTheadMac ISA extension new 75047aeb7e6 riscv: thead: Add support for the XTheadFmv ISA extension new 02fcaf412ae riscv: thead: Add support for the XTheadMemPair ISA extension

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 26 ++ gcc/config.gcc | 1 + gcc/config/riscv/bitmanip.md | 52 ++- gcc/config/riscv/constraints.md | 8 + gcc/config/riscv/iterators.md | 4 + gcc/config/riscv/peephole.md | 56 +++ gcc/config/riscv/riscv-cores.def | 4 + gcc/config/riscv/riscv-opts.h | 26 ++ gcc/config/riscv/riscv-protos.h | 16 +- gcc/config/riscv/riscv.cc | 226 ++++++++--- gcc/config/riscv/riscv.md | 67 +++- gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/t-riscv | 4 + gcc/config/riscv/thead.cc | 427 +++++++++++++++++++++ gcc/config/riscv/thead.md | 346 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c | 28 ++ gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c | 55 +++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 20 + gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c | 22 ++ gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c | 22 ++ gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c | 18 + gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 45 +++ gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c | 25 ++ gcc/testsuite/gcc.target/riscv/xtheadbb.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadbs.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 14 + .../gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c | 38 ++ .../gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c | 38 ++ .../gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c | 38 ++ .../gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c | 38 ++ .../riscv/xtheadcondmov-mvnez-imm-cond.c | 38 ++ .../gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c | 38 ++ .../riscv/xtheadcondmov-mvnez-reg-cond.c | 38 ++ .../gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c | 38 ++ gcc/testsuite/gcc.target/riscv/xtheadcondmov.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 24 ++ gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 + .../gcc.target/riscv/xtheadmac-mula-muls.c | 43 +++ gcc/testsuite/gcc.target/riscv/xtheadmac.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 14 + gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c | 98 +++++ gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c | 84 ++++ gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c | 29 ++ gcc/testsuite/gcc.target/riscv/xtheadmempair.c | 13 + gcc/testsuite/gcc.target/riscv/xtheadsync.c | 14 + 49 files changed, 2196 insertions(+), 67 deletions(-) create mode 100644 gcc/config/riscv/thead.cc create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ff1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac-mula-muls.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c