[gcc] branch master updated (f2d7a4001a3 -> 1b4c70d4271) - Tcwg-commits

6 Sep 2023


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unknown user pushed a change to branch master
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from  f2d7a4001a3 analyzer: implement kf_strstr [PR105899]
       new  ee21f79f729 RISC-V: Remove unreasonable TARGET_64BIT for VLS modes with [...]
       new  1b4c70d4271 RISC-V: Fix VSETVL PASS AVL/VL fetch bug[111295]
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Summary of changes:
 gcc/config/riscv/riscv-vector-switch.def           |  8 ++---
 gcc/config/riscv/riscv-vsetvl.cc                   |  3 +-
 .../gcc.target/riscv/rvv/autovec/partial/slp-9.c   |  2 +-
 .../gcc.target/riscv/rvv/autovec/pr111295.c        | 36 ++++++++++++++++++++++
 .../riscv/rvv/autovec/zve32f_zvl1024b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl128b-1.c           |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl2048b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl256b-1.c           |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl4096b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32f_zvl512b-1.c           |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl1024b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl128b-1.c           |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl2048b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl256b-1.c           |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl4096b-1.c          |  2 +-
 .../riscv/rvv/autovec/zve32x_zvl512b-1.c           |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64d-1.c        |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64f-1.c        |  2 +-
 .../gcc.target/riscv/rvv/autovec/zve64x-1.c        |  2 +-
 19 files changed, 57 insertions(+), 22 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111295.c
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