This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch master in repository gcc.

from d324d56221d RISC-V: Finalize testcases for final version VSETVL PASS. new ab39fa8c8fd RISC-V: Add vlm/vsm C/C++ API intrinsics support new 931a042f7e6 RISC-V: Add vle.v C API intrinsics testcases new 4f6d7f9b6ad RISC-V: Add vse.v C API intrinsics testcases new ce34fa309e0 RISC-V: Fix vop_m overloaded C++ API name. new c17082867eb RISC-V: Add vle/vse C++ overloaded API intrinsic testcases new 3caa3a3f1a0 RISC-V: Fix testcases check.

The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/riscv-vector-builtins-bases.cc | 6 +- gcc/config/riscv/riscv-vector-builtins-bases.h | 2 + .../riscv/riscv-vector-builtins-functions.def | 2 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 7 +- gcc/config/riscv/riscv-vector-builtins-types.def | 15 + gcc/config/riscv/riscv-vector-builtins.cc | 43 +- gcc/config/riscv/vector.md | 23 +- .../riscv/rvv/base/riscv_vector.h | 0 gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C | 345 +++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vle_tu-1.C | 345 +++++++++++ .../g++.target/riscv/rvv/base/vle_tum-1.C | 345 +++++++++++ .../g++.target/riscv/rvv/base/vle_tumu-1.C | 345 +++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vse-1.C | 685 +++++++++++++++++++++ gcc/testsuite/g++.target/riscv/rvv/base/vsm-1.C | 40 ++ .../g++.target/riscv/{riscv.exp => rvv/rvv.exp} | 14 +- gcc/testsuite/gcc.target/riscv/rvv/base/vle-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle-3.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-3.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-1.c | 344 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-2.c | 344 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-3.c | 344 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tum-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tum-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tum-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tumu-1.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tumu-2.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vle_tumu-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/base/vlm_vsm-1.c | 75 +++ .../gcc.target/riscv/rvv/base/vlm_vsm-2.c | 75 +++ .../gcc.target/riscv/rvv/base/vlm_vsm-3.c | 75 +++ gcc/testsuite/gcc.target/riscv/rvv/base/vse-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vse-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vse-3.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-1.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-2.c | 345 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-3.c | 345 +++++++++++ .../gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c | 2 +- .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c | 3 +- 45 files changed, 10713 insertions(+), 13 deletions(-) copy gcc/testsuite/{gcc.target => g++.target}/riscv/rvv/base/riscv_vector.h (100%) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vle_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vse-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsm-1.C copy gcc/testsuite/g++.target/riscv/{riscv.exp => rvv/rvv.exp} (69%) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlm_vsm-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vse_m-3.c