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from 82e912344d2 Fortran: Fix ICE in ASSOCIATE with user defined operator [P [...] new c02fa90cb32 aarch64: Use SVE2 NBSL for vector NOR and NAND for Advanced [...] new 2ae2203da59 aarch64: Use SVE2 BSL2N for vector EON new 9041f2bff82 RISC-V: Fix vsetvl merge rule. new 4648fe556e2 expand: Allow fixed-point arithmetic for RDIV_EXPR.

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Summary of changes: gcc/cfgexpand.cc | 3 +- gcc/config/aarch64/aarch64-sve2.md | 63 ++++++++++++++++++++ gcc/config/riscv/riscv-vsetvl.def | 6 +- gcc/optabs-tree.cc | 3 +- gcc/testsuite/gcc.target/aarch64/sve2/eon_bsl2n.c | 52 +++++++++++++++++ .../gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c | 68 ++++++++++++++++++++++ gcc/testsuite/gcc.target/arm/pr121065.c | 11 ++++ gcc/testsuite/gcc.target/riscv/rvv/pr120297.c | 50 ++++++++++++++++ 8 files changed, 251 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/eon_bsl2n.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c create mode 100644 gcc/testsuite/gcc.target/arm/pr121065.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/pr120297.c