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unknown user pushed a change to branch hjl/iamcu/improve in repository gcc.
discards 58c2737 Also check configure.ac in binutils source tree discards 6eee3be IA MCU run-time doesn't support TLS discards 3f1d45d Skip incompatible tests on IA MCU target discards 2af5384 Turn off loop and funcion alignments for IA MCU discards 3242af8 Turn on X86_TUNE_USE_BT for IA MCU discards e190dde Turn off X86_TUNE_ZERO_EXTEND_WITH_AND for IA MCU discards 3208292 Skip error_mark_node type decls discards f57ca46 Add __builtin_ia32_stack_top adds a93d7f2 * doc/invoke.texi (Language Independent Options): Rename nod [...] adds 0146686 gcc/ChangeLog: adds 3061044 2015-07-22 Richard Biener rguenther@suse.de adds bf3bbdf 2015-07-22 Charles Baylis charles.baylis@linaro.org adds ace499f 2015-07-22 Richard Biener rguenther@suse.de adds a46441d 2015-07-22 Chung-Lin Tang cltang@codesourcery.com adds 18be45a [AArch64] PR target/63521 Define REG_ALLOC_ORDER adds 606d0d6 Add -march=interaptiv. adds 68fb434 Add scheduling for M51xx core family. adds 4d289e2 2015-07-22 Richard Biener rguenther@suse.de adds cfa66ec 2015-07-22 Richard Biener rguenther@suse.de adds 6059989 [Patch ARM/AArch64 obvious] Fix typo: Rename insn_reservation [...] adds c70b874 Fix r225926's iso_varying_string ICE regression adds 7794f2c * config/nvptx/nvptx.c: Expand some comments. adds 53c2dd6 Add __builtin_stack_top new 3bcc9ee Skip error_mark_node type decls new 2d52d81 Turn off X86_TUNE_ZERO_EXTEND_WITH_AND for IA MCU new fb4e43b Turn on X86_TUNE_USE_BT for IA MCU new cc32de6 Turn off loop and funcion alignments for IA MCU new 5fb6d8c Skip incompatible tests on IA MCU target new 1a62f92 IA MCU run-time doesn't support TLS new eb0038e Also check configure.ac in binutils source tree
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Summary of changes: gcc/ChangeLog | 120 +++++++++ gcc/builtin-types.def | 1 + gcc/builtins.c | 11 + gcc/builtins.def | 1 + gcc/config/aarch64/aarch64-builtins.c | 30 ++- gcc/config/aarch64/aarch64-simd-builtins.def | 12 +- gcc/config/aarch64/aarch64-simd.md | 74 +++--- gcc/config/aarch64/aarch64.h | 25 ++ gcc/config/aarch64/arm_neon.h | 276 ++++++++++---------- gcc/config/arm/cortex-a53.md | 2 +- gcc/config/i386/i386.c | 28 +-- gcc/config/i386/i386.h | 4 - gcc/config/mips/m5100.md | 220 ++++++++++++++++ gcc/config/mips/mips-cpus.def | 4 + gcc/config/mips/mips-tables.opt | 45 ++-- gcc/config/mips/mips.c | 13 + gcc/config/mips/mips.h | 13 +- gcc/config/mips/mips.md | 2 + gcc/config/nvptx/nvptx.c | 29 ++- gcc/doc/extend.texi | 10 +- gcc/doc/invoke.texi | 12 +- gcc/doc/tm.texi | 5 + gcc/doc/tm.texi.in | 2 + gcc/fortran/ChangeLog | 7 + gcc/fortran/trans-array.c | 6 +- gcc/function.h | 3 + gcc/genmatch.c | 142 +++++------ gcc/ipa-pure-const.c | 1 + gcc/target.def | 7 + gcc/targhooks.c | 9 + gcc/targhooks.h | 3 + gcc/testsuite/ChangeLog | 278 +++++++++++++++++++++ gcc/testsuite/gcc.dg/torture/pr66952.c | 28 +++ .../advsimd-intrinsics/vld2_lane_f32_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_f64_indices_1.c | 17 ++ .../advsimd-intrinsics/vld2_lane_p8_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_s16_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_s32_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_s64_indices_1.c | 17 ++ .../advsimd-intrinsics/vld2_lane_s8_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_u16_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_u32_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2_lane_u64_indices_1.c | 17 ++ .../advsimd-intrinsics/vld2_lane_u8_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2q_lane_f32_indices_1.c | 16 ++ .../advsimd-intrinsics/vld2q_lane_f64_indices_1.c | 17 ++ .../advsimd-intrinsics/vld2q_lane_p8_indices_1.c | 17 ++ .../advsimd-intrinsics/vld2q_lane_s16_indices_1.c | 16 ++ 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.../advsimd-intrinsics/vst4_lane_u16_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4_lane_u32_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4_lane_u64_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4_lane_u8_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_f32_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_f64_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4q_lane_p8_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4q_lane_s16_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_s32_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_s64_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4q_lane_s8_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4q_lane_u16_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_u32_indices_1.c | 15 ++ .../advsimd-intrinsics/vst4q_lane_u64_indices_1.c | 16 ++ .../advsimd-intrinsics/vst4q_lane_u8_indices_1.c | 16 ++ gcc/testsuite/gcc.target/i386/pr66960-1.c | 2 +- gcc/testsuite/gcc.target/i386/pr66960-2.c | 2 +- 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