[gcc] branch master updated (e3da1d7bb28 -> 5de05bdaa71) - Tcwg-commits

31 Oct 2023


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from  e3da1d7bb28 tree-optimization/112305 - SCEV cprop and conditional undef [...]
       new  15404016d96 hardcfr: support checking at abnormal edges [PR111943]
       new  184378027e9 genemit: Split insn-emit.cc into several partitions.
       new  5de05bdaa71 RISC-V: Add vector fmin/fmax expanders.
The 3 revisions listed above as "new" are entirely new to this
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Summary of changes:
 gcc/Makefile.in                                    |  36 +-
 gcc/config/riscv/autovec.md                        |  72 +++
 gcc/config/riscv/riscv-v.cc                        |   2 +
 gcc/config/riscv/vector-iterators.md               |   8 +
 gcc/config/riscv/vector.md                         |  43 ++
 gcc/configure                                      |  24 +-
 gcc/configure.ac                                   |  13 +
 gcc/genemit.cc                                     | 542 ++++++++++++---------
 gcc/gensupport.cc                                  |  55 +++
 gcc/gensupport.h                                   |   1 +
 gcc/gimple-harden-control-flow.cc                  |  78 ++-
 gcc/read-md.cc                                     |   4 +-
 gcc/read-md.h                                      |   2 +-
 gcc/testsuite/gcc.dg/harden-cfr-pr111943.c         |  33 ++
 .../gcc.target/riscv/rvv/autovec/binop/fmax-1.c    |  24 +
 .../riscv/rvv/autovec/binop/fmax_run-1.c           |  47 ++
 .../riscv/rvv/autovec/binop/fmax_zvfh-1.c          |  23 +
 .../riscv/rvv/autovec/binop/fmax_zvfh_run-1.c      |  48 ++
 .../gcc.target/riscv/rvv/autovec/binop/fmin-1.c    |  10 +
 .../{cond/cond_fmin_run-1.c => binop/fmin_run-1.c} |   4 +-
 .../{cond/cond_fmin-4.c => binop/fmin_zvfh-1.c}    |   8 +-
 .../riscv/rvv/autovec/binop/fmin_zvfh_run-1.c      |   5 +
 .../riscv/rvv/autovec/cond/cond_fmax-1.c           |   6 +-
 .../riscv/rvv/autovec/cond/cond_fmax-2.c           |   3 +-
 .../riscv/rvv/autovec/cond/cond_fmax-3.c           |   6 +-
 .../riscv/rvv/autovec/cond/cond_fmax-4.c           |   6 +-
 .../riscv/rvv/autovec/cond/cond_fmax_run-1.c       |   3 +-
 .../riscv/rvv/autovec/cond/cond_fmax_run-2.c       |   3 +-
 .../riscv/rvv/autovec/cond/cond_fmax_run-3.c       |   3 +-
 .../riscv/rvv/autovec/cond/cond_fmax_run-4.c       |   3 +-
 .../cond/{cond_fmax-1.c => cond_fmax_zvfh-1.c}     |   9 +-
 .../cond/{cond_fmax-2.c => cond_fmax_zvfh-2.c}     |   8 +-
 .../cond/{cond_fmax-3.c => cond_fmax_zvfh-3.c}     |   9 +-
 .../cond/{cond_fmax-4.c => cond_fmax_zvfh-4.c}     |   9 +-
 .../{cond_fmax_run-1.c => cond_fmax_zvfh_run-1.c}  |   7 +-
 .../{cond_fmax_run-2.c => cond_fmax_zvfh_run-2.c}  |   7 +-
 .../{cond_fmax_run-3.c => cond_fmax_zvfh_run-3.c}  |   7 +-
 .../{cond_fmax_run-4.c => cond_fmax_zvfh_run-4.c}  |   7 +-
 .../riscv/rvv/autovec/cond/cond_fmin-1.c           |   5 +-
 .../riscv/rvv/autovec/cond/cond_fmin-2.c           |   3 +-
 .../riscv/rvv/autovec/cond/cond_fmin-3.c           |   5 +-
 .../riscv/rvv/autovec/cond/cond_fmin-4.c           |   5 +-
 .../riscv/rvv/autovec/cond/cond_fmin_run-1.c       |   2 +-
 .../riscv/rvv/autovec/cond/cond_fmin_run-2.c       |   2 +-
 .../riscv/rvv/autovec/cond/cond_fmin_run-3.c       |   2 +-
 .../riscv/rvv/autovec/cond/cond_fmin_run-4.c       |   2 +-
 .../cond/{cond_fmin-2.c => cond_fmin_zvfh-1.c}     |   7 +-
 .../cond/{cond_fmin-2.c => cond_fmin_zvfh-2.c}     |   7 +-
 .../cond/{cond_fmin-2.c => cond_fmin_zvfh-3.c}     |   7 +-
 .../cond/{cond_fmin-2.c => cond_fmin_zvfh-4.c}     |   7 +-
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c  |   5 +
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c  |   5 +
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c  |   5 +
 .../riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c  |   5 +
 .../gcc.target/riscv/rvv/autovec/reduc/reduc-10.c  |  26 +
 .../riscv/rvv/autovec/reduc/reduc_run-10.c         |  41 ++
 .../riscv/rvv/autovec/reduc/reduc_zvfh-10.c        |  24 +
 .../riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c    |  41 ++
 libgcc/hardcfr.c                                   |   2 +-
 59 files changed, 1053 insertions(+), 333 deletions(-)
 create mode 100644 gcc/testsuite/gcc.dg/harden-cfr-pr111943.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmax_zvfh_run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin-1.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{cond/cond_fmin_run-1.c => binop/f [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/{cond/cond_fmin-4.c => binop/fmin_ [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/fmin_zvfh_run-1.c
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax-1.c => cond_fmax_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax-2.c => cond_fmax_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax-3.c => cond_fmax_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax-4.c => cond_fmax_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax_run-1.c => cond_fm [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax_run-2.c => cond_fm [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax_run-3.c => cond_fm [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmax_run-4.c => cond_fm [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmin-2.c => cond_fmin_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmin-2.c => cond_fmin_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmin-2.c => cond_fmin_z [...]
 copy gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/{cond_fmin-2.c => cond_fmin_z [...]
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_fmin_zvfh_run-4.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_run-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh-10.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_zvfh_run-10.c
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