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from b34ced6c7d4 [X86] Add load folding isel patterns to scalar_math_pattern [...] new a813b38069d Change semantics of fadd/fmul vector reductions.

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Summary of changes: docs/LangRef.rst | 58 ++- include/llvm/CodeGen/BasicTTIImpl.h | 20 +- include/llvm/IR/Intrinsics.td | 16 +- lib/CodeGen/ExpandReductions.cpp | 57 +-- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 18 +- lib/IR/AutoUpgrade.cpp | 43 ++- lib/IR/IRBuilder.cpp | 4 +- lib/Transforms/Utils/LoopUtils.cpp | 12 +- test/Assembler/invalid-vecreduce.ll | 24 +- test/Bitcode/upgrade-vecreduce-intrinsics.ll | 64 ++++ test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc | Bin 0 -> 1860 bytes .../CodeGen/AArch64/vecreduce-fadd-legalization.ll | 28 +- test/CodeGen/AArch64/vecreduce-fadd.ll | 32 +- .../Generic/expand-experimental-reductions.ll | 32 +- test/CodeGen/X86/haddsub.ll | 71 ++-- test/CodeGen/X86/vector-reduce-fadd-fast.ll | 414 ++++++++++++--------- test/CodeGen/X86/vector-reduce-fadd.ll | 64 ++-- test/CodeGen/X86/vector-reduce-fmul-fast.ll | 282 +++++++------- test/CodeGen/X86/vector-reduce-fmul.ll | 64 ++-- 19 files changed, 744 insertions(+), 559 deletions(-) create mode 100644 test/Bitcode/upgrade-vecreduce-intrinsics.ll create mode 100644 test/Bitcode/upgrade-vecreduce-intrinsics.ll.bc