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unknown user pushed a change to branch master in repository gcc.

from fbad7a74aaa libstdc++: Fix tests with non-const operator== new 5576518a566 RISC-V: Add RVV registers register spilling

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Summary of changes: gcc/config/riscv/riscv-v.cc | 47 +-- gcc/config/riscv/riscv.cc | 147 ++++++-- gcc/config/riscv/riscv.h | 3 + gcc/config/riscv/vector-iterators.md | 23 ++ gcc/config/riscv/vector.md | 136 ++++++-- gcc/testsuite/gcc.target/riscv/rvv/base/macro.h | 6 + gcc/testsuite/gcc.target/riscv/rvv/base/spill-1.c | 385 +++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c | 41 +++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c | 60 ++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c | 47 +++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-2.c | 320 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-3.c | 254 ++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-4.c | 196 +++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-5.c | 130 +++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-6.c | 101 ++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-7.c | 114 ++++++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c | 51 +++ gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c | 42 +++ 18 files changed, 2017 insertions(+), 86 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/macro.h create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c