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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/llvm-project.

from d38a0258a5f [AArch64] Add patterns for FMCLA*_indexed. adds 060cfd97954 [AArch64][SVE]Add cost model for masked gather and scatter [...] adds 4d7cb6da9fc [Sparc] SparcMCExpr::printVariantKind - fix Wcovered-switch [...] adds 82a29a62aba [OpenMP] Add definition/interface for target memory routines adds 9f8c0d15c7f DeclCXX - Fix getAs<> null-dereference static analyzer warn [...] adds e9f401d8a26 [IR] CallBase::getBundleOpInfoForOperand - ensure Current i [...] adds ed936aad781 [InterleavedAccess] Return correct 'modified' status. adds e2d3d501ef8 [RISCV][NFC] Add additional cmov tests adds c367258b5cc [SimplifyCFG] Enabled hoisting late in LTO pipeline. adds c55b609b777 [Hexagon] Fix bad SDNodeXForm adds 76bfbb74d38 [libomptarget][amdgpu] Call into deviceRTL instead of ockl adds f7463ca3cc5 [ProfileData] GCOVFile::readGCNO - silence undefined pointe [...] adds fe5d51a4897 [OpenMP] Add using bit flags to select Libomptarget Information adds dd6bb367d19 [LoopDeletion] Break backedge of loops when known not taken adds 7c63aac7bd4 Revert "[LoopDeletion] Break backedge of loops when known n [...] adds d8938c8bb54 CodeGen: Use Register adds 6976812129b [InstCombine] add tests for ashr+icmp; NFC adds dc9ac0e8207 [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) ise [...] adds b8f22f9d300 [NewPM][AMDGPU] Run InternalizePass when -amdgpu-internaliz [...] adds 848e8f938fd [llvm] Construct SmallVector with iterator ranges (NFC) adds 0edbc90ec56 [DebugInfo] Use llvm::append_range (NFC) adds eb198f4c3ce [llvm] Use llvm::any_of (NFC) adds a5f863e0765 [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late adds e1833e7493a [NewPM][AMDGPU] Port amdgpu-unify-metadata adds 9a17bff4f71 [LoopNest] Allow empty basic blocks without loops adds 4034f9273ed Switching Clang UniqueInternalLinkageNamesPass scheduling t [...] adds 4d0aad96e43 [flang][openmp] Make Reduction clause part of OmpClause adds fe597efc30b [RISCV] Remove unused method RISCVInstPrinter::printSImm5Pl [...] adds fd323a897c6 [NewPM][AMDGPU] Port amdgpu-printf-runtime-binding adds 4e838ba9ea2 [NewPM][AMDGPU] Port amdgpu-always-inline adds 191552344bb [NewPM][AMDGPU] Make amdgpu-aa work with NewPM adds de6d43f16cb Revert "[LoopNest] Allow empty basic blocks without loops" adds 92be640bd7d [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when [...] adds 58b6c5d932a [LoopUtils] reorder logic for creating reduction; NFC adds 97669575241 [LoopUtils] reduce code for creatng reduction; NFC adds aa169033892 [test] Pin backedge-id-bug-xfail.ll to legacy PM adds 8e293fe6ad0 [NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass adds abbef2fd46d [ValueTracking] isGuaranteedNotToBePoison should return tru [...] adds efc82c4ad2b [NFC, Refactor] Modernize StorageClass from Specifiers.h to [...] adds 36263a7cccc [LoopUtils] remove redundant opcode parameter; NFC adds 2fd11e0b1ef Revert "[NFC, Refactor] Modernize StorageClass from Specifi [...] adds f67d3dbdb93 [clang] - Also look for devtoolset-10 adds b4f519bddda [NFCI] DwarfEHPrepare: update DomTree in non-permissive mod [...] adds 3fb57222c4c [NFCI] SimplifyCFG: switch to non-permissive DomTree update [...] adds ed9de61cc3e [SimplifyCFGPass] mergeEmptyReturnBlocks(): switch to non-p [...] adds a8604e3d5b7 [SimplifyCFG] simplifyIndirectBr(): switch to non-permissiv [...] adds 110b3d7855e [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor [...] adds 32c47ebef18 [SimplifyCFG] SimplifyCondBranchToTwoReturns(): switch to n [...] adds e30fbbe9a53 [JumpThreading][NewPM] Skip when target has divergent CF adds c4f12a07a44 [WebAssembly] Remove old SDT_WebAssemblyCalls (NFC) adds f28b026d32c [InstSimplify] add a test for gep with poison operand (NFC) adds f665a8c5b8b [InstSimplify] gep with poison operand is poison adds ae614851631 [UpdateTestChecks] Fix PowerPC RE to support AIX assembly adds d51d72bbb91 [RISCV] Rename RVV intrinsics class (NFC) adds 2962f1149c8 [NFC] Add the getSizeInBytes() interface for MachineConstan [...] adds 48340fbe6a1 [NFC] [PowerPC] Update vec_constants test to reflect more patterns adds b6c8feb29fc [NFC] [PowerPC] Remove dead code in BUILD_VECTOR peephole adds 3e2b42489f8 Remove RefSCC::handleTrivialEdgeInsertion adds 854b861881a [llvm/Orc] Fix ExecutionEngine module build breakage adds 979c38cc74f [compiler-rt] [windows] Add UNUSED attributes on variables/ [...] adds 3c1d015edc7 [GlobalISel][TableGen] Fix ConstrainOperandRC bug adds 2654f33c47f [VE] Support llvm.eh.sjlj.lsda adds 1d4411e9ea0 [RISCV] Add vector integer min/max ISel patterns adds 6725860d21a Sema::BuildCallExpr - use cast<> instead of dyn_cast<> for [...] adds 52e448974b2 SystemZTargetLowering::lowerDYNAMIC_STACKALLOC - use cast<> [...] adds 84d5768d976 MemProfiler::insertDynamicShadowAtFunctionEntry - use cast< [...] adds 02eb8e20b51 Inform the consumer on invalid template instantiations. adds 53a341a61d1 [VE][NFC] Fix typo in comments adds 9ad83fd6dc4 [WebAssembly] call_indirect causes indirect function table import adds 914066fe38a [DebugInfo] Avoid LSR crash on large integer inputs adds 7a97eeb197a [Coroutines] checkAsyncFuncPointer - use cast<> instead of [...] adds a000366d050 [SimplifyIndVar] createWideIV - make WideIVInfo arg a const [...] adds 38c6933dcc9 [LV] Simplify lambda in all_of to directly return hasVF() r [...] adds eba6deab22b [SVE] Lower vector CTLZ, CTPOP and CTTZ operations. adds 313d982df65 [IR] Add ConstantInt::getBool helpers to wrap getTrue/getFalse. adds f784be0777f [VE] Support SJLJ exception related instructions adds 0e4d2361b81 [OpenCL] Warn about side effects for unevaluated vec_step arg adds 2f8d1e9eb27 [clangd] When querying drivers by binary, look in PATH too adds 4e6054a86c0 [AMDGPU] Split out new helper function macToMad in SIFoldOp [...] adds 639a50e2f13 [AMDGPU] Precommit test case for D94010 adds 3914bebe91f [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands new 9a1ac97d3af [CodeGen] Format SelectionDAG::getConstant methods (NFC) new 489000d8516 [VE] Change clang to support SjLj Lowering new dc74d7ed1f6 [X86] getMemoryOpCost - use dyn_cast_or_null<StoreInst>. NFCI. new 6f770292a00 [OpenCL] Restrict pointer to member functions.

The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: clang-tools-extra/clangd/QueryDriverDatabase.cpp | 24 +- .../clangd/test/system-include-extractor.test | 31 +- clang/lib/AST/DeclCXX.cpp | 6 +- clang/lib/Basic/Targets/VE.h | 5 +- clang/lib/CodeGen/BackendUtil.cpp | 6 +- clang/lib/CodeGen/CGOpenMPRuntimeAMDGCN.cpp | 7 +- clang/lib/Driver/ToolChains/Gnu.cpp | 1 + clang/lib/Sema/SemaDecl.cpp | 4 +- clang/lib/Sema/SemaExpr.cpp | 24 +- clang/lib/Sema/SemaTemplateInstantiate.cpp | 4 +- clang/test/OpenMP/amdgcn_target_codegen.cpp | 10 +- clang/test/Sema/builtin-longjmp.c | 1 + clang/test/SemaCXX/coroutines.cpp | 2 + clang/test/SemaOpenCL/vec_step.cl | 2 + clang/test/SemaOpenCLCXX/members.cl | 22 + compiler-rt/lib/interception/interception_win.cpp | 6 +- flang/lib/Parser/openmp-parsers.cpp | 4 +- flang/lib/Parser/unparse.cpp | 2 - flang/lib/Semantics/check-omp-structure.cpp | 2 +- flang/lib/Semantics/check-omp-structure.h | 2 +- llvm/include/llvm/Analysis/IVDescriptors.h | 9 +- llvm/include/llvm/Analysis/LazyCallGraph.h | 4 - llvm/include/llvm/Analysis/TargetTransformInfo.h | 11 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 5 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 6 +- llvm/include/llvm/CodeGen/LiveInterval.h | 7 +- llvm/include/llvm/CodeGen/MachineConstantPool.h | 6 +- llvm/include/llvm/CodeGen/MachineFrameInfo.h | 7 +- llvm/include/llvm/DebugInfo/CodeView/TypeRecord.h | 2 +- llvm/include/llvm/Frontend/OpenMP/OMP.td | 2 +- llvm/include/llvm/IR/Constants.h | 2 + llvm/include/llvm/IR/DebugInfoMetadata.h | 5 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 16 +- llvm/include/llvm/IR/Metadata.h | 3 +- llvm/include/llvm/IR/PredIteratorCache.h | 2 +- llvm/include/llvm/Transforms/Utils/LoopUtils.h | 3 +- .../include/llvm/Transforms/Utils/SimplifyIndVar.h | 2 +- llvm/include/llvm/module.modulemap | 6 +- llvm/lib/Analysis/IVDescriptors.cpp | 5 +- llvm/lib/Analysis/InstructionSimplify.cpp | 9 +- llvm/lib/Analysis/LazyCallGraph.cpp | 23 - llvm/lib/Analysis/ScalarEvolution.cpp | 16 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 4 + llvm/lib/Analysis/ValueTracking.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 3 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 +- llvm/lib/CodeGen/InterleavedAccessPass.cpp | 25 +- llvm/lib/CodeGen/MachineFunction.cpp | 12 +- llvm/lib/CodeGen/MachineSink.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 21 +- llvm/lib/DebugInfo/DWARF/DWARFDie.cpp | 3 +- llvm/lib/DebugInfo/MSF/MSFBuilder.cpp | 6 +- llvm/lib/DebugInfo/PDB/Native/NamedStreamMap.cpp | 2 +- llvm/lib/DebugInfo/PDB/Native/SymbolCache.cpp | 3 +- llvm/lib/DebugInfo/PDB/Native/TpiStreamBuilder.cpp | 2 +- .../ExecutionEngine/Orc/TargetProcessControl.cpp | 8 +- llvm/lib/IR/Constants.cpp | 10 +- llvm/lib/IR/Instructions.cpp | 2 +- llvm/lib/IR/Verifier.cpp | 4 +- llvm/lib/MC/WasmObjectWriter.cpp | 7 + llvm/lib/Passes/PassBuilder.cpp | 10 +- llvm/lib/ProfileData/GCOV.cpp | 2 +- llvm/lib/Support/SourceMgr.cpp | 2 +- llvm/lib/TableGen/Record.cpp | 4 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 43 + llvm/lib/Target/AArch64/AArch64ISelLowering.h | 3 + llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 19 +- .../Target/AArch64/AArch64TargetTransformInfo.cpp | 20 + .../Target/AArch64/AArch64TargetTransformInfo.h | 11 + llvm/lib/Target/AArch64/SVEInstrFormats.td | 14 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 40 + llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 2 + llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h | 7 +- llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp | 20 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 2 +- .../Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp | 77 +- .../Target/AMDGPU/AMDGPUPropagateAttributes.cpp | 19 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 70 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp | 59 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 53 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonPatterns.td | 2 +- llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 11 - .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 9 - .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.h | 2 - llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 6 + llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp | 75 +- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 4 +- llvm/lib/Target/VE/VEISelLowering.cpp | 751 ++++++++++++- llvm/lib/Target/VE/VEISelLowering.h | 56 +- llvm/lib/Target/VE/VEInstrBuilder.h | 41 + llvm/lib/Target/VE/VEInstrInfo.td | 38 + .../WebAssembly/AsmParser/WebAssemblyAsmParser.cpp | 27 + .../lib/Target/WebAssembly/WebAssemblyFastISel.cpp | 11 + .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 10 + .../lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 2 - .../Target/WebAssembly/WebAssemblyUtilities.cpp | 19 + llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h | 8 + llvm/lib/Target/X86/X86MCInstLower.cpp | 5 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 5 +- llvm/lib/Transforms/Coroutines/Coroutines.cpp | 4 +- llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 6 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 8 +- .../lib/Transforms/Instrumentation/MemProfiler.cpp | 2 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 4 + llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 5 +- llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 7 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 112 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 107 +- llvm/lib/Transforms/Utils/SimplifyIndVar.cpp | 2 +- .../Vectorize/LoopVectorizationPlanner.h | 4 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 6 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +- .../AArch64/sve-getIntrinsicInstrCost-gather.ll | 37 + .../AArch64/sve-getIntrinsicInstrCost-scatter.ll | 40 + llvm/test/CodeGen/AArch64/sve-bit-counting.ll | 173 +++ .../AArch64/sve-fixed-length-bit-counting.ll | 1128 ++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 2 + llvm/test/CodeGen/AMDGPU/clamp-modifier.ll | 2 +- llvm/test/CodeGen/AMDGPU/clamp.ll | 4 +- llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll | 8 +- llvm/test/CodeGen/AMDGPU/fma-combine.ll | 4 +- llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 42 +- .../force-alwaysinline-lds-global-address.ll | 2 + llvm/test/CodeGen/AMDGPU/fpext-free.ll | 2 +- llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 4 +- llvm/test/CodeGen/AMDGPU/internalize.ll | 4 +- llvm/test/CodeGen/AMDGPU/known-never-snan.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll | 85 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll | 4 +- .../CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll | 1 + llvm/test/CodeGen/AMDGPU/mad-combine.ll | 6 +- llvm/test/CodeGen/AMDGPU/mad-mix.ll | 8 +- llvm/test/CodeGen/AMDGPU/opencl-printf.ll | 1 + .../CodeGen/AMDGPU/propagate-attributes-clone.ll | 2 + .../propagate-attributes-flat-work-group-size.ll | 1 + .../AMDGPU/propagate-attributes-single-set.ll | 1 + llvm/test/CodeGen/AMDGPU/rcp-pattern.ll | 4 +- llvm/test/CodeGen/AMDGPU/rsq.ll | 2 +- llvm/test/CodeGen/AMDGPU/unify-metadata.ll | 1 + llvm/test/CodeGen/AMDGPU/v_mac.ll | 6 +- llvm/test/CodeGen/AMDGPU/v_mac_f16.ll | 12 +- .../CodeGen/Hexagon/isel-splat-vector-neg-i8.ll | 16 + llvm/test/CodeGen/PowerPC/aix-lr.ll | 40 +- llvm/test/CodeGen/PowerPC/vec_constants.ll | 89 +- llvm/test/CodeGen/RISCV/rv32Zbt.ll | 560 ++++++++-- llvm/test/CodeGen/RISCV/rv64Zbt.ll | 260 ++++- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll | 871 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll | 843 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll | 871 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll | 843 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll | 871 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll | 843 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll | 871 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll | 843 +++++++++++++++ llvm/test/CodeGen/RISCV/vararg.ll | 48 +- llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll | 213 ++++ llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll | 87 ++ .../CodeGen/VE/Scalar/builtin_sjlj_callsite.ll | 282 +++++ .../CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll | 303 ++++++ llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll | 16 + llvm/test/CodeGen/VE/Scalar/sjlj_except.ll | 32 - llvm/test/CodeGen/WebAssembly/call-indirect.ll | 28 + llvm/test/MC/WebAssembly/type-index.s | 8 + llvm/test/TableGen/GlobalISelEmitterSubreg.td | 5 + llvm/test/Transforms/InstCombine/icmp-shr.ll | 419 +++++++- llvm/test/Transforms/InstSimplify/gep.ll | 12 +- .../X86/interleave-load-extract-shuffle-changes.ll | 58 + .../JumpThreading/divergent-target-test.ll | 2 + .../LoopStrengthReduce/dbg-preserve-1.ll | 73 ++ .../StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll | 2 +- .../Inputs/ppc_generated_funcs.ll | 1 + .../ppc_generated_funcs.ll.generated.expected | 60 ++ .../ppc_generated_funcs.ll.nogenerated.expected | 60 ++ llvm/tools/llvm-readobj/ELFDumper.cpp | 5 +- llvm/tools/opt/opt.cpp | 12 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 4 + llvm/utils/TableGen/AsmMatcherEmitter.cpp | 5 +- llvm/utils/TableGen/CodeGenTarget.cpp | 7 +- llvm/utils/TableGen/CodeGenTarget.h | 3 +- llvm/utils/TableGen/GICombinerEmitter.cpp | 8 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 3 +- llvm/utils/UpdateTestChecks/asm.py | 11 +- .../deviceRTLs/amdgcn/src/amdgcn_interface.h | 2 + .../deviceRTLs/amdgcn/src/target_impl.hip | 6 +- openmp/libomptarget/include/Debug.h | 44 +- openmp/libomptarget/include/SourceInfo.h | 9 +- openmp/libomptarget/plugins/cuda/src/rtl.cpp | 28 +- openmp/libomptarget/src/device.cpp | 23 +- openmp/libomptarget/src/interface.cpp | 42 +- openmp/libomptarget/src/private.h | 63 +- openmp/libomptarget/test/offloading/info.c | 35 +- openmp/runtime/src/include/omp.h.var | 18 + openmp/runtime/src/include/omp_lib.f90.var | 97 ++ openmp/runtime/src/include/omp_lib.h.var | 107 ++ 205 files changed, 13009 insertions(+), 962 deletions(-) create mode 100644 clang/test/SemaOpenCLCXX/members.cl create mode 100644 llvm/lib/Target/VE/VEInstrBuilder.h create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...] create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-bit-counting.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-fixed-length-bit-counting.ll create mode 100644 llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/builtin_sjlj.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/builtin_sjlj_bp.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/builtin_sjlj_callsite.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/builtin_sjlj_landingpad.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/builtin_sjlj_lsda.ll delete mode 100644 llvm/test/CodeGen/VE/Scalar/sjlj_except.ll create mode 100644 llvm/test/CodeGen/WebAssembly/call-indirect.ll create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extr [...] create mode 100644 llvm/test/Transforms/LoopStrengthReduce/dbg-preserve-1.ll