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from 60f58d06308 Objective-C/C++: Ensure sufficient setup for the preprocessor. new d05b5265110 RISC-V: Introduce XTheadVector as a subset of V1.0.0 new 9a55cc625c5 RISC-V: Adds the prefix "th." for the instructions of XThea [...] new 2d7205eb2c3 RISC-V: Handle differences between XTheadvector and Vector new 0a41c3e49af RISC-V: Add support for xtheadvector-specific intrinsics. new cdf4729f088 RISC-V: Fix register overlap issue for some xtheadvector in [...] new 9e1b554cc75 RISC-V: Rewrite some instructions using ASM targethook

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 23 ++ gcc/config.gcc | 2 +- gcc/config/riscv/autovec.md | 2 +- gcc/config/riscv/predicates.md | 4 +- gcc/config/riscv/riscv-c.cc | 11 +- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-string.cc | 3 +- gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 187 ++++++++++- gcc/config/riscv/riscv-vector-builtins-bases.h | 31 ++ gcc/config/riscv/riscv-vector-builtins-shapes.cc | 183 +++++++++++ gcc/config/riscv/riscv-vector-builtins-shapes.h | 3 + gcc/config/riscv/riscv-vector-builtins.cc | 70 ++++ gcc/config/riscv/riscv-vector-builtins.h | 3 + gcc/config/riscv/riscv-vector-switch.def | 150 ++++----- gcc/config/riscv/riscv.cc | 31 +- gcc/config/riscv/riscv.h | 4 + gcc/config/riscv/riscv.md | 22 ++ gcc/config/riscv/riscv.opt | 2 + .../riscv/{riscv_vector.h => riscv_th_vector.h} | 22 +- gcc/config/riscv/t-riscv | 1 + .../riscv/thead-vector-builtins-functions.def | 39 +++ gcc/config/riscv/thead-vector.md | 352 ++++++++++++++++++++ gcc/config/riscv/thead.cc | 239 ++++++++++++++ gcc/config/riscv/vector.md | 357 +++++++++++++-------- .../riscv/predef-__riscv_th_v_intrinsic.c | 11 + gcc/testsuite/gcc.target/riscv/rvv/base/abi-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pragma-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c | 13 + .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 + .../gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c | 68 ++++ .../gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c | 68 ++++ .../gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c | 68 ++++ .../gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c | 68 ++++ .../gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c | 68 ++++ .../gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c | 68 ++++ gcc/testsuite/lib/target-supports.exp | 12 + 37 files changed, 1950 insertions(+), 255 deletions(-) copy gcc/config/riscv/{riscv_vector.h => riscv_th_vector.h} (71%) create mode 100644 gcc/config/riscv/thead-vector-builtins-functions.def create mode 100644 gcc/config/riscv/thead-vector.md create mode 100644 gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c