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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project.

from 27fe841aa65 AMDGPU: Refine rcp/rsq intrinsic folding for modern FP rules adds cdd006eec94 SimplifyCFG: Clean up optforfuzzing implementation adds fe0006c882f TargetLowering.h - remove unnecessary TargetMachine.h include. NFC adds 2833c46f75a [DwarfEHPrepare] Don't prune unreachable resumes at optnone adds 8d041811983 [ValueTracking] Use assumptions in computeConstantRange. adds 2e43bab1c16 [docs] Fix warnings in ConstantInterpreter adds f2ffa33c79d [lldb/Interpreter] Fix another eExpressionThreadVanished warning adds c3116182c80 Revert "[lldb/Interpreter] Fix another eExpressionThreadVan [...] adds a521532aa16 [NFC] Remove non-variadic overloads of allocator_traits::co [...] adds de172ef61ea [CFIInstrInserter] Delete unneeded checks adds 6e48a6e407b [libcxx] Fix deprecation warning by suppressing deprecated [...] adds b631f86ac5b [TLI][PowerPC] Introduce TLI query to check if MULH is chea [...] adds 9292ece9956 [clang driver] Spell "--export-dynamic-symbol" with two dashes. adds 088fb973484 [NFC, StackSafety] LTO tests for MTE and StackSafety adds 99660217e93 [AArch64][GlobalISel] When generating SUBS for compares, do [...] adds cc65a7a5ea8 [X86] Improve i8 + 'slow' i16 funnel shift codegen adds 79401230840 [X86] Fix typo in comment. NFC adds 2bb822bc902 [X86] Add family/model for Intel Comet Lake CPUs for -march [...] adds 8310c9b7410 [X86][AVX] Call SimplifyDemandedBits on MaskedLoadSDNode wi [...] adds f794808bb9e [LLD/MinGW]: Expose --thinlto-cache-dir adds 04d32d7ac18 X86TargetMachine.h - remove unnecessary X86Subtarget forwar [...] adds ffb367217d6 [X86] Move CONCAT_VECTORS/INSERT_SUBVECTOR actions inside l [...] adds 72210ce7f57 Fix Wdocumentation warnings after argument renaming. NFC. adds 16031067252 [TargetLowering] Improve expandFunnelShift shift amount masking adds 478f2ce5d3c [X86] Pull out repeated DemandedBits signmask variable. NFC. adds d0f2a8a0492 X86Subtarget.h - remove unnecessary TargetMachine.h include. NFC. adds 5e9392deaf5 Add explicit traversal mode to matchers for implicit constructors adds 04ed532ef0c Fix skip-invisible with overloaded method calls adds 3ed8ebc2f6b Fix return values of some matcher functions adds 510b0f42371 LoopSimplify.h - reduce unnecessary includes to forward dec [...] adds a6502560628 AMDGPULibFunc - fix include order. NFC. adds 725b3463c53 AMDGPUTargetObjectFile.h - remove unnecessary includes. NFC. adds 15224408f0d [VPlan] Use VPUser for VPWidenSelectRecipe operands (NFC). adds b05b69e056a AMDGPUInstPrinter.cpp - add CommandLine.h include. NFC. adds 7eed772a279 [PatternMatch] abbreviate vector inst matchers; NFC adds c048a02b5b2 [InstCombine] fold FP trunc into exact itofp adds 4c5818dd8cd [clang-tidy] Fix potential assert in use-noexcept check adds 86e3abc9e63 [PowerPC] Add some InstAlias definitions adds 71bed8206b3 AMDGPU.h - reduce TargetMachine.h include. NFC. adds 1e7865d9464 [X86] SimplifyMultipleUseDemandedBitsForTargetNode - add in [...] adds d43fac052e1 [PhaseOrdering] adjust test to use default alias analysis w [...] adds 0deab8a54fd [LV] Either get invariant condition OR vector condition. adds 57bb4787d72 [Pass Manager] remove EarlyCSE as clean-up for VectorCombine adds e508d643cfd [X86][AVX] Fold extract_subvector(broadcast(x),c) -> extrac [...] new 8a5aea7b504 [X86][AVX] Fold extract_subvector(subv_broadcast(x),c) -> (x)

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: .../clang-tidy/bugprone/StringConstructorCheck.cpp | 3 +- .../bugprone/StringLiteralWithEmbeddedNulCheck.cpp | 4 +- .../clang-tidy/modernize/UseNoexceptCheck.cpp | 25 +- .../clang-tidy/modernize/UseNoexceptCheck.h | 2 +- .../readability/RedundantStringInitCheck.cpp | 5 +- .../checkers/modernize-use-noexcept-error.cpp | 6 + clang/docs/ConstantInterpreter.rst | 50 +- clang/include/clang/ASTMatchers/ASTMatchers.h | 4 +- clang/lib/AST/Expr.cpp | 6 +- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- .../lib/StaticAnalyzer/Checkers/MallocChecker.cpp | 18 +- clang/test/Driver/memtag_lto.c | 143 ++++ clang/test/Driver/sanitizer-ld.c | 2 +- clang/unittests/AST/ASTTraverserTest.cpp | 49 ++ compiler-rt/lib/builtins/cpu_model.c | 2 + libcxx/include/memory | 79 +- lld/MinGW/Driver.cpp | 2 + lld/MinGW/Options.td | 2 + lld/test/ELF/ppc32-call-stub-pic.s | 2 +- lld/test/MinGW/driver.test | 3 + llvm/include/llvm/Analysis/ValueTracking.h | 5 +- llvm/include/llvm/CodeGen/Passes.h | 3 +- llvm/include/llvm/CodeGen/TargetLowering.h | 6 +- llvm/include/llvm/IR/PatternMatch.h | 8 +- llvm/include/llvm/Transforms/Utils/Local.h | 18 +- llvm/include/llvm/Transforms/Utils/LoopSimplify.h | 8 +- llvm/lib/Analysis/InstructionSimplify.cpp | 6 +- llvm/lib/Analysis/ValueTracking.cpp | 33 +- llvm/lib/Analysis/VectorUtils.cpp | 6 +- llvm/lib/CodeGen/Analysis.cpp | 1 + llvm/lib/CodeGen/AsmPrinter/WinException.cpp | 1 + llvm/lib/CodeGen/CFIInstrInserter.cpp | 8 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 5 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 19 +- llvm/lib/CodeGen/ExpandMemCmp.cpp | 1 + llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 1 + llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp | 1 + llvm/lib/CodeGen/LiveDebugValues.cpp | 1 + llvm/lib/CodeGen/LowerEmuTLS.cpp | 1 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 1 + .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 1 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 +- llvm/lib/CodeGen/SwitchLoweringUtils.cpp | 1 + llvm/lib/CodeGen/TargetPassConfig.cpp | 4 +- llvm/lib/CodeGen/TypePromotion.cpp | 1 + llvm/lib/LTO/UpdateCompilerUsed.cpp | 1 + llvm/lib/Passes/PassBuilder.cpp | 1 - llvm/lib/Support/Host.cpp | 2 + llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 8 +- .../Target/AArch64/AArch64InstructionSelector.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 3 +- .../Target/AMDGPU/AMDGPUFixFunctionBitcasts.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h | 1 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 1 + llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPULibFunc.h | 1 + llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp | 1 + llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h | 2 - .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 1 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 +- llvm/lib/Target/ARM/ARMSubtarget.h | 1 + llvm/lib/Target/ARM/MVETailPredication.cpp | 8 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 + llvm/lib/Target/PowerPC/PPCISelLowering.h | 5 + llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 18 + llvm/lib/Target/PowerPC/PPCInstrHTM.td | 5 + llvm/lib/Target/PowerPC/PPCInstrInfo.td | 31 + llvm/lib/Target/Sparc/SparcTargetObjectFile.cpp | 1 + llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp | 1 + llvm/lib/Target/SystemZ/SystemZSubtarget.cpp | 1 + llvm/lib/Target/SystemZ/SystemZTDC.cpp | 1 + .../Target/WebAssembly/WebAssemblyCFGStackify.cpp | 1 + .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 1 + .../WebAssembly/WebAssemblyMachineFunctionInfo.cpp | 1 + llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 89 +- llvm/lib/Target/X86/X86IndirectThunks.cpp | 1 + llvm/lib/Target/X86/X86MCInstLower.cpp | 1 + .../lib/Target/X86/X86SpeculativeLoadHardening.cpp | 1 + llvm/lib/Target/X86/X86Subtarget.cpp | 4 + llvm/lib/Target/X86/X86Subtarget.h | 2 +- llvm/lib/Target/X86/X86TargetMachine.h | 1 - llvm/lib/Target/X86/X86TargetObjectFile.cpp | 1 + llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 8 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 91 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 6 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 2 +- .../InstCombine/InstCombineVectorOps.cpp | 28 +- .../InstCombine/InstructionCombining.cpp | 26 +- llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 8 + llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 18 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 26 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 4 +- llvm/lib/Transforms/Vectorize/VPlan.h | 12 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 24 +- .../AArch64/GlobalISel/opt-fold-compare.mir | 10 +- .../GlobalISel/select-arith-immed-compare.mir | 8 +- .../test/CodeGen/AArch64/GlobalISel/select-cmp.mir | 2 +- llvm/test/CodeGen/AArch64/GlobalISel/select.mir | 6 +- llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir | 2 +- llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir | 2 +- llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 - llvm/test/CodeGen/AMDGPU/opt-pipeline.ll | 3 - .../PowerPC/2007-04-30-InlineAsmEarlyClobber.ll | 2 +- llvm/test/CodeGen/PowerPC/2009-09-18-carrybit.ll | 4 +- llvm/test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 2 +- .../PowerPC/CompareEliminationSpillIssue.ll | 2 +- llvm/test/CodeGen/PowerPC/atomics-regression.ll | 60 +- llvm/test/CodeGen/PowerPC/crbits.ll | 6 +- llvm/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll | 2 +- .../test/CodeGen/PowerPC/expand-contiguous-isel.ll | 4 +- llvm/test/CodeGen/PowerPC/expand-isel.ll | 2 +- llvm/test/CodeGen/PowerPC/f128-compare.ll | 12 +- llvm/test/CodeGen/PowerPC/fast-isel-binary.ll | 6 +- llvm/test/CodeGen/PowerPC/fold-remove-li.ll | 2 +- llvm/test/CodeGen/PowerPC/fold-zero.ll | 6 +- llvm/test/CodeGen/PowerPC/funnel-shift.ll | 8 +- .../CodeGen/PowerPC/handle-f16-storage-type.ll | 2 +- llvm/test/CodeGen/PowerPC/htm.ll | 10 +- llvm/test/CodeGen/PowerPC/i1-ext-fold.ll | 8 +- llvm/test/CodeGen/PowerPC/i64_fp_round.ll | 2 +- llvm/test/CodeGen/PowerPC/ifcvt.ll | 4 +- llvm/test/CodeGen/PowerPC/inc-of-add.ll | 12 +- .../CodeGen/PowerPC/loop-instr-form-prepare.ll | 9 +- llvm/test/CodeGen/PowerPC/machine-pre.ll | 14 +- llvm/test/CodeGen/PowerPC/memcmp.ll | 8 +- llvm/test/CodeGen/PowerPC/mul-const.ll | 6 +- llvm/test/CodeGen/PowerPC/noPermuteFormasking.ll | 6 +- llvm/test/CodeGen/PowerPC/optcmp.ll | 20 +- llvm/test/CodeGen/PowerPC/optimize-andiso.ll | 2 +- .../CodeGen/PowerPC/pcrel-call-linkage-leaf.ll | 8 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 16 +- llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll | 4 +- llvm/test/CodeGen/PowerPC/ppc64-P9-mod.ll | 8 +- llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll | 4 +- llvm/test/CodeGen/PowerPC/pr44183.ll | 2 +- .../CodeGen/PowerPC/remove-redundant-load-imm.ll | 2 +- llvm/test/CodeGen/PowerPC/sat-add.ll | 60 +- llvm/test/CodeGen/PowerPC/select_const.ll | 56 +- llvm/test/CodeGen/PowerPC/setcc-logic.ll | 6 +- llvm/test/CodeGen/PowerPC/shift128.ll | 2 +- llvm/test/CodeGen/PowerPC/signbit-shift.ll | 12 +- llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 6 +- llvm/test/CodeGen/PowerPC/sms-phi-2.ll | 14 +- llvm/test/CodeGen/PowerPC/spe.ll | 18 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 12 +- llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 950 +++++++++------------ llvm/test/CodeGen/PowerPC/stack-guard-reassign.ll | 2 +- llvm/test/CodeGen/PowerPC/stack-realign.ll | 12 +- llvm/test/CodeGen/PowerPC/store-combine.ll | 4 +- llvm/test/CodeGen/PowerPC/sub-of-not.ll | 12 +- llvm/test/CodeGen/PowerPC/subc.ll | 2 +- llvm/test/CodeGen/PowerPC/subreg-postra.ll | 2 +- .../PowerPC/umulo-128-legalisation-lowering.ll | 4 +- llvm/test/CodeGen/PowerPC/urem-lkk.ll | 10 +- llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll | 924 +++++++++----------- .../PowerPC/use-cr-result-of-dom-icmp-st.ll | 40 +- llvm/test/CodeGen/PowerPC/vec-min-max.ll | 8 +- llvm/test/CodeGen/PowerPC/vsx.ll | 12 +- llvm/test/CodeGen/X86/O0-pipeline.ll | 1 - llvm/test/CodeGen/X86/avx2-masked-gather.ll | 2 - llvm/test/CodeGen/X86/avx512-vbroadcasti256.ll | 12 +- llvm/test/CodeGen/X86/fshl.ll | 102 +-- llvm/test/CodeGen/X86/fshr.ll | 118 ++- llvm/test/CodeGen/X86/masked_load.ll | 9 - llvm/test/CodeGen/X86/movmsk-cmp.ll | 4 - llvm/test/CodeGen/X86/oddshuffles.ll | 20 +- llvm/test/CodeGen/X86/pr18014.ll | 9 +- llvm/test/CodeGen/X86/pr45443.ll | 16 +- llvm/test/CodeGen/X86/pr45563-2.ll | 22 - llvm/test/CodeGen/X86/rotate-extract.ll | 28 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 200 ++--- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 188 ++-- llvm/test/CodeGen/X86/vector-rotate-256.ll | 20 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-lshr-256.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-256.ll | 5 +- .../MC/Disassembler/PowerPC/ppc64-encoding-ext.txt | 16 +- .../Disassembler/PowerPC/ppc64-encoding-p8htm.txt | 8 +- .../MC/Disassembler/PowerPC/ppc64-encoding.txt | 12 +- .../MC/Disassembler/PowerPC/ppc64le-encoding.txt | 12 +- llvm/test/MC/PowerPC/htm.s | 16 +- llvm/test/MC/PowerPC/ppc64-encoding.s | 20 +- llvm/test/MC/PowerPC/ppc64-operands.s | 24 +- llvm/test/Other/new-pm-defaults.ll | 1 - llvm/test/Other/new-pm-thinlto-defaults.ll | 1 - .../Other/new-pm-thinlto-postlink-pgo-defaults.ll | 1 - .../new-pm-thinlto-postlink-samplepgo-defaults.ll | 1 - llvm/test/Other/opt-O2-pipeline.ll | 1 - llvm/test/Other/opt-O3-pipeline.ll | 1 - llvm/test/Other/opt-Os-pipeline.ll | 1 - llvm/test/Transforms/InstCombine/fptrunc.ll | 5 +- llvm/test/Transforms/LoopVectorize/X86/optsize.ll | 60 +- .../LoopVectorize/float-minmax-instruction-flag.ll | 21 +- llvm/test/Transforms/PhaseOrdering/X86/addsub.ll | 35 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 182 +++- llvm/unittests/IR/PatternMatch.cpp | 51 +- 199 files changed, 2448 insertions(+), 2328 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/modernize-use-noexce [...] create mode 100644 clang/test/Driver/memtag_lto.c