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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/gcc.
from a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix adds cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian adds 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] adds cd0b7124273 c++: Fix parsing of invalid enum specifiers [PR90995] adds 046c58907ec c: Handle C_TYPE_INCOMPLETE_VARS even for ENUMERAL_TYPEs [PR94172] adds 2e30d3e3e88 testsuite: Fix g++.dg/debug/dwarf2/const2b.C target selector adds 3b2cc34369a Daily bump. adds 98f29f5638f libstdc++: Fix type-erasure in experimental::net::executor [...] adds 80616e5b7a5 c++: Fix comment typo. adds 52b3aa8be18 dwarf: Generate DIEs for external variables with -g1 [93751] adds af8656be8df c++: Diagnose a deduction guide in a wrong scope [PR91759] adds 4e3d3e40726 middle-end/94188 fix fold of addr expression generation adds 4da9288745d libgomp testsuite - disable long double for AMDGCN adds cb26919c857 aarch64: Treat p12-p15 as call-preserved in SVE PCS functions adds d91480dee93 aarch64: Fix SYMBOL_TINY_GOT handling for ILP32 [PR94201] adds d5029d45940 Fix up duplicated duplicated words in comments adds 1ba9acb11e3 middle-end/94206 fix memset folding to avoid types with padding adds 11cf25c40e3 PR c++/94147 - mangling of lambdas assigned to globals adds 5a80a6c3e5f amdgcn: Add cond_add/sub/and/ior/xor for all vector modes adds dbde9e2d595 amdgcn: Fix vector compare modes adds 07522ae90b5 libstdc++: Fix compilation with released versions of Clang adds e5de406f996 libstdc++ Fix compilation of <stop_token> with Clang adds 0db2cd17702 analyzer: tweaks to exploded_node ctor adds 7d9c107ab1e analyzer: introduce noop_region_model_context adds f665beeba62 analyzer: add test coverage for fixed ICE [PR94047] adds 884d9141112 analyzer: make summarized dumps more comprehensive adds 26cbcfe5fce Fix libgomp.oacc-fortran/atomic_capture-1.f90 adds 8165795c155 [ARM][GCC][2/3x]: MVE intrinsics with ternary operands. adds e3678b4464a [ARM][GCC][3/3x]: MVE intrinsics with ternary operands. adds db5db9d2548 [ARM][GCC][1/4x]: MVE intrinsics with quaternary operands. adds 8eb3b6b9cf2 [ARM][GCC][2/4x]: MVE intrinsics with quaternary operands. adds f2170a379b0 [ARM][GCC][3/4x]: MVE intrinsics with quaternary operands. adds 532e9e2402a [ARM][GCC][4/4x]: MVE intrinsics with quaternary operands. adds 4ff68575991 [ARM][GCC][1/5x]: MVE store intrinsics. adds 535a8645bb8 [ARM][GCC][2/5x]: MVE load intrinsics. adds 405e918c314 [ARM][GCC][3/5x]: MVE store intrinsics with predicated suffix. adds 429d607bc46 [ARM][GCC][4/5x]: MVE load intrinsics with zero(_z) suffix. adds bf1e3d5afa1 [ARM][GCC][5/5x]: MVE ACLE load intrinsics which load a byt [...] adds 4cc23303bad [ARM][GCC][6/5x]: Remaining MVE load intrinsics which loads [...] adds 5cad47e0f85 [ARM][GCC][7/5x]: MVE store intrinsics which stores byte,ha [...] adds 7a5fffa5ed0 [ARM][GCC][8/5x]: Remaining MVE store intrinsics which stor [...] adds 3512dc0108a PR ipa/92799 - ICE on a weakref function definition followe [...] adds 529ea7d9596 Complete change to resolve pr90275. adds 07fe4af4d51 rs6000: Add back some w* constraints (PR91886) adds b3341826531 libstdc++: Fix is_trivially_constructible (PR 94033) adds b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] adds 75fb811dfaa Verify the code used for the optimized comparison is valid [...] adds c86c99e6950 Update gcc es.po, sv.po. adds 75c24a08d69 Daily bump. adds 047811579f0 cgraphunit: Avoid code generation differences based on -w/T [...] adds a5a9400a846 if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283] adds 565ab7efbdc loop-manip: Avoid -fcompare-debug issues in create_iv [PR94285] adds 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] adds 906b3eb9df6 Improve endianess detection. adds c2211a60ff0 Fix OpenMP offload handling for target-link variables for n [...] adds 04099157691 Define __BIG_ENDIAN__ adds 8001f59c82b [testsuite,arm] target-supports.exp: Add arm_fp_dp_ok effec [...] adds 2a0eaca3e9c [testsuite,arm] cmp-2.c: Move double-precision tests to cmp-3.c adds 07f8bcc6ea9 [testsuite,arm] use arm_fp_dp_ok effective-target adds 6e771c087b1 c++: Give more expressions locations. adds 5c161741843 c++: Fix template parm with dependent type in concepts. adds fddfd3ce555 c++: Improve handling of ill-formed constraints [PR94186]. adds 75b7b7fdc45 c++: Fix wrong no post-decrement operator error in template [...] adds 0c1c8d9f137 Daily bump. adds adaf4b6c66e Test for sigsetjmp support in analyzer tests requiring that [...] adds c2133167ad5 if-conv: Delete dead stmts backwards in ifcvt_local_dce [PR94283] adds f1154b4d3c5 sccvn: Fix buffer overflow in push_partial_def [PR94300] adds 158cccea0d0 middle-end: Avoid using DECL_UID in ASM_FORMAT_PRIVATE_NAME [...] adds 5f18995e23e varasm: Fix output_constructor where a RANGE_EXPR index nee [...] adds c38daa79768 fortran: ICE using undeclared symbol in array constructor PR93484 adds c8504ebef1d testsuite: Fix up FAILs in gfortran testsuite with -fcompar [...] adds 0fb0240a051 Fix handling of --with{,out}-zstd option. adds 724ec02c2c6 Make target_clones resolver fn static if possible. adds d5ad8ee04a7 i386: Fix ix86_add_reg_usage_to_vzeroupper [PR94308] adds 780f1cfd8ee testsuite: Mention cleanup-13.c test is incompatible with - [...] adds 68c4570a4de Do not error about missing zstd unless --with-zstd. adds 83dfa06cb5c coroutines: Fix missing dereference (PR94319). adds 0fca105f8ca Fix gcc.dg/pr92301.c on targets that don't support argc/argv. adds 05c13c43990 PR tree-optimization/94131 - ICE on printf with a VLA strin [...] adds c7a252ba2d0 c++: Fix invalid -Wduplicated-cond warning [PR94265] adds 713ecb3d417 rs6000: Allow FPRs to change between SDmode and DDmode [...] adds b5228b1bc8c PR middle-end/94004 - missing -Walloca on calls to alloca d [...] adds 6e4cd3cd259 arm: Fix ICE caused by arm_gen_dicompare_reg [PR94292] adds eeb0c7c0713 Fix vector-compare-1 regressions on sh4/sh4eb caused by pat [...] adds 48817fbd761 Fix vector-compare-1 regressions on sh4/sh4eb caused by [...] adds fe4b53b2e7e testsuite: adjustments for amdgcn adds bf1fc37bb4a libstdc++: Define and use chrono::is_clock for C++20 adds e3ef371982a libstdc++ Add missing tests for std::shared_timed_mutex adds 9673d11ec53 libstdc++: Fix author in previous ChangeLog entry adds e97929e20b2 [PATCH] rs6000: vec_rlnm fix to make builtin work according to ABI adds 27f8c8c4c92 Daily bump. adds d21dff5b4fe widening_mul: restrict ops to be defined in the same basic- [...] adds 9708ca2be40 var-tracking: Mark as sp based more VALUEs [PR92264] adds 5a1706f63a2 c++: Fix a -fcompare-debug issue with DEBUG_BEGIN_STMT stmt [...] adds dab932d1519 c++: Fix up user_provided_p [PR81349] adds 10ea09ee846 gimplify: Fix -fcompare-debug differences caused by gimplif [...] adds d6730f06420 Skip test for non-x86 targets. adds da920d0c46c tree: Fix -fcompare-debug issues due to protected_set_expr_ [...] adds 40cdcddf274 Fix UNRESOLVED test-case. adds e519d644999 arm: unified syntax for libgcc when built with -Os [PR94220] adds 16948c54b75 libstdc++: Add some C++20 additions to <chrono> adds 2a1f0f64160 coroutines: Implement n4849 changes to exception handling. adds 6d85947d23a coroutines: Implement n4849 recommended symmetric transfer. adds 517f5356bb0 c++: DR1710, template keyword in a typename-specifier [PR94057] adds b1c905ba83e Update gcc .po files. adds f9c38702e96 Daily bump. adds 65937db83cd coroutines, testsuite: Fix symmetric-transfer-00-basic.C on Linux. adds 54f58e9416d c++: Remove redundant calls to type_dependent_expression_p adds 71d69548a1b c++: template keyword accepted before destructor names [PR94336] adds 06d5d63d994 modulo-sched: fix bootstrap compare-debug issue adds 72809d6fe8e c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 2eea00c518d c++: Avoid calls in non-evaluated contexts affect whether f [...] adds a76ff304f90 Fortran] Reject invalid association target (PR93363) adds a9cd2d786ad fixup: move ChangeLog entry for last Arm fix to correct file. adds 66e0e23c12d fixup: move ChangeLog entry for last Arm fix to correct file. adds 8d689cf43b5 Fix PR90332 by extending half size vector mode adds 62ede14d30f [Fortran] Fix ICE with deferred-rank arrays (PR93957) adds 917e21e8bcd tree-optimization/94352 - fix uninitialized use of curr_order adds 45cfaf9903d debug/94273 - avoid creating type DIEs for DINFO_LEVEL_TERSE adds 4d661bb7a2e analyzer: tweaks to superedge::dump adds 8f02357571a analyzer: improvements to diagnostic-manager.cc logging adds 42c63313252 analyzer: add new supergraph visualization adds 6969ac301f2 analyzer: fix malloc pointer NULL-ness adds 9dba60130dc c++: Fix ICE after ambiguous inline namespace reopen [PR94257] adds 04dd734b52d c++: avoid -Wredundant-tags on a first declaration in use [ [...] adds 038769535a8 amdgcn: refactor mode iterators adds ccacf77be55 PR c++/94098 - ICE on attribute access redeclaration adds c7fc15f54b3 [pr84733] Fix ICE popping local scope adds 52f24a9e989 PR c++/94346 - [9/10 Regression] ICE due to handle_copy_att [...] adds 54de5afb4a9 c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 19e5389debb [RS6000] PR94145, make PLT loads volatile adds 491009b609d Update gcc de.po. adds 0302a2de7f1 libstdc++: Move definition earlier in file adds ae6076b5bc1 libstdc++: Implement C++20 changes to insert iterators adds 81a8d137c22 libstdc++: Add remaining C++20 changes to iterator adaptors adds b8a28a06eaf libstdc++: Define __cpp_lib_ranges macro for C++20 adds c2781192292 Daily bump. adds 679becf175c reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329] adds c6a562de88c c: After issuing errors about array size, for error-recover [...] adds 75defde9fb5 c++: Replay errors during diagnosis of constraint satisfact [...] adds cd68edf894d c++: Respect current_constraint_diagnosis_depth in diagnose [...] adds a7ea3d2ced7 c++: requires-expression outside of a template is misevalua [...] adds 7981c06ae92 c++: Diagnose when "requires" is used instead of "requires [...] adds 3fb7f2fbd5f [Fortran] Fix result-variable handling of MODULE PROCEDURE [...] adds 7d57570b065 Patch for PR94246 adds 946a444df34 testsuite: adjust modulo-sched compare-debug tests adds 42cda3ba45f libstdc++: Fix std::reverse_iterator relational operators adds f6b2b79040d libstdc++: Fix two tests that fail in C++20 mode adds 673bb288e62 Daily bump. adds c76df72f1a9 testsuite: Split up gdc-test.exp into each subdirectory adds 46b7d819f7c Delete duplicate .align output. adds 85f6f317ec8 Fix typo in a warning related to flatten. adds afd9da8b8ad testsuite: Move C++ tests in gdc.test into own subdirectory. adds 60c254b279e testsuite: Handle more kinds of gdc.test test flags and dir [...] adds dacc7effeea doc: Update -falign-functions/-falign-loops/-falign-jumps adds 2a93fb6e962 Daily bump. adds 07c48b61a08 [RS6000] Put call cookie back in AIX/ELFv2 call patterns adds ec919cfcef8 Fix vextract* masked patterns [PR93069] adds 3a9db91bee4 Fix scan pattern of vect-8.f90 dump. adds 291aa50a631 XFAIL pr57193.c test-case. adds 5abbfd3cd36 i386: Fix up *one_cmplv*2* insn with avx512f [PR94343] adds 48c18af43fa Update bswap64-4 test for desired results adds 841e721579b RS6000 Allow builtin initialization regardless of mask adds 48e331d6382 Define TRY_EMPTY_VM_SPACE for riscv64-linux adds 1cb1986cb59 c++: Fix handling of internal fn calls in statement express [...] adds 5830f753559 c++: Fix comparison of fn() and ns::fn() [PR90711] adds 9f6abd1b03e Update gcc sv.po. adds 13a29fc5730 Daily bump. adds 3809bcd6c0e lra: set insn_code_data to NULL when freeing adds 56f0b32476c forwprop: Pattern recognize more rotates [PR94344] adds 5ea39b24122 store-merging: Allow enums during bswap recognition [PR94403] adds 1dcffc8ddc4 fold-const: Fix division folding with vector operands [PR94412] adds a27c534794d aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368] adds e81d0d9ec7a [ARM][PATCH]: Add support for MVE ACLE intrinsics polymorph [...] adds cea1fc6f67d arc: Allow more ABIs in GLIBC_DYNAMIC_LINKER adds 1ef979c6966 [ARM][PATCH]: Add MVE ACLE intrinsics vbicq_n_* polymorphic [...] adds d08a318b4fd arc: Cleanup compilation warning adds dc56917d111 arc: Update operand printing adds 1165109b401 amdgcn: generalize vector insn modes adds 48742e02d71 d: Use d_comdat_linkage on generated internal decl. adds e06cde870ed Library-side tests for parenthesized aggregate init adds f14b41d2712 vect: ICE: in vectorizable_load, at tree-vect-stmts.c:9173 [...] adds e8e0acbaa38 d: Use memset to fill alignment holes with zeroes. adds 331c438d5a6 Update cpplib sr.po. adds 689418b97e5 libgomp – fix handling of 'target enter data' adds 63b2923dc6f libgccjit: add new version entry point adds 1c16f7fc903 d: Add always_inline to the internal attribute table. adds 013fca64fc1 d: Merge UDAs between function prototype and definitions (PR90136) adds 73dd051894b Daily bump. adds 595f1b1274b c++: Adjust formatting. adds 76f09260b7e c++: Fix DMI with lambda 'this' capture [PR94205] adds bd0f22a8d5c Fix PR94043 by making vect_live_op generate lc-phi adds 142d68f50b4 Fix typo in a macro usage. adds 9ecb3ecc8cc objsz: Don't call replace_uses_by on SSA_NAME_OCCURS_IN_ABN [...] adds d3ee88fdb4e Clear me from patch ownership. adds 0c9a8a8c103 fortran : FAIL: gfortran.dg/pr93365.f90 PR94386 adds e899d4b7125 Add testcase for already fixed PR [PR94436] adds 032f2366a4c rs6000: Make code questionably using r2 not ICE (PR94420) adds dd5da571731 doc: Fix a typo in the documentation of the copy attribute adds 43d011eb054 Whoops, forgot the changelog adds b60bd122dc7 doc: Fix typo adds 7546463b9f7 subreg: Fix PR94123, SVN r273240 causes gcc.target/powerpc/ [...] adds a96f1c38a78 analyzer: handle compound assignments [PR94378] adds 6c557ba5380 libstdc++: Move "free books" list from fsf.org to gnu.org adds fb25041e11d d: Fix gdc.dg/pr92216.d FAILs on 32-bit targets adds 918b89b7623 d: Fix new tests gdc.dg/pr93038.d and gdc.dg/pr93038b.d in [...] adds 25839b6af9f Daily bump. adds bf1f6d8819a fortran: ICE equivalence with an element of an array PR94030 adds 2c54eab5a30 fortran : ICE in gfc_resolve_findloc PR93498 adds b7a98f48e06 S/390: Remove superfluous commutative constraint modifiers adds 224efaf7e1e [Fortran] Fix error cleanup of select rank (PR93522) adds c1effaa209f libstdc++-v3/test: Better skip for "use_service.cc" adds ff825b81583 [ARM]: Fix for MVE ACLE intrinsics with writeback (PR94317). adds 66e327517b1 aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] adds df562b12d90 aarch64: Fix ICE due to aarch64_gen_compare_reg_maybe_ze [PR94435] adds 2c0fa3ecf70 cselib: Reuse VALUEs on sp adjustments [PR92264] adds 86c92411320 params: Decrease -param=max-find-base-term-values= default [...] adds d4ed2cd13d0 sra/doc: Document param sra-max-propagations adds 68cbee9bf53 Fix up -Wliteral-suffix warning on mti-linux.h adds 81ce375d1fd Fix PR94401 by considering reverse overrun adds 879bc686a0a doc: RISC-V: Update binutils requirement to 2.30
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 7619 ++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 196 + gcc/analyzer/analyzer.h | 1 + gcc/analyzer/checker-path.cc | 1 + gcc/analyzer/constraint-manager.cc | 1 + gcc/analyzer/diagnostic-manager.cc | 50 +- gcc/analyzer/diagnostic-manager.h | 32 + gcc/analyzer/engine.cc | 287 +- gcc/analyzer/exploded-graph.h | 31 +- gcc/analyzer/program-point.cc | 1 + gcc/analyzer/program-state.cc | 3 +- gcc/analyzer/region-model.cc | 638 +- gcc/analyzer/region-model.h | 171 +- gcc/analyzer/sm-malloc.cc | 2 +- gcc/analyzer/state-purge.cc | 21 +- gcc/analyzer/state-purge.h | 5 +- gcc/analyzer/supergraph.cc | 56 +- gcc/analyzer/supergraph.h | 19 +- gcc/asan.c | 7 +- gcc/c-family/ChangeLog | 30 + gcc/c-family/c-attribs.c | 35 +- gcc/c-family/c-common.c | 11 +- gcc/c-family/c-warn.c | 5 + gcc/c-family/c.opt | 4 + gcc/c/ChangeLog | 39 + gcc/c/c-decl.c | 57 +- gcc/c/c-parser.c | 52 +- gcc/c/c-tree.h | 14 +- gcc/c/c-typeck.c | 3 +- gcc/calls.c | 82 +- gcc/cgraph.c | 90 +- gcc/cgraph.h | 17 +- gcc/cgraphunit.c | 32 +- gcc/config/aarch64/aarch64.c | 53 +- gcc/config/aarch64/aarch64.md | 22 +- gcc/config/aarch64/atomics.md | 5 +- gcc/config/aarch64/constraints.md | 7 + gcc/config/aarch64/iterators.md | 3 +- gcc/config/arc/arc.c | 8 +- gcc/config/arc/arc.h | 6 +- gcc/config/arc/linux.h | 3 +- gcc/config/arm/arm-builtins.c | 455 + gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.c | 27 +- gcc/config/arm/arm.md | 15 +- gcc/config/arm/arm_mve.h | 27052 ++++++++++++++++++- gcc/config/arm/arm_mve_builtins.def | 828 + gcc/config/arm/constraints.md | 43 +- gcc/config/arm/iterators.md | 11 + gcc/config/arm/mve.md | 10629 +++++++- gcc/config/arm/neon.md | 53 +- gcc/config/arm/predicates.md | 36 + gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 75 +- gcc/config/arm/vfp.md | 7 +- gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/gcn/gcn-valu.md | 2113 +- gcc/config/gcn/gcn.h | 4 + gcc/config/gcn/gcn.md | 2 + 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+ .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 21 + 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.../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 19 + .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 21 + 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+ .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 22 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 21 + .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 22 + .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 22 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 22 + .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 21 + .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 13 + .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vctp16q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp32q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp64q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 22 + .../gcc.target/arm/mve/intrinsics/vctp8q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 22 + .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 22 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 22 + .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 22 + .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 23 + .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 23 + 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.../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 21 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 22 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 25 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 25 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 21 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 23 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 24 + .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 21 + .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 15 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 15 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 15 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 15 + .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 13 + .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 21 + .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 21 + .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 21 + .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 21 + .../vldrdq_gather_shifted_offset_z_s64.c | 21 + .../vldrdq_gather_shifted_offset_z_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 13 + .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 21 + .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 21 + .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 21 + .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 21 + .../vldrhq_gather_shifted_offset_z_f16.c | 21 + .../vldrhq_gather_shifted_offset_z_s16.c | 21 + .../vldrhq_gather_shifted_offset_z_s32.c | 21 + .../vldrhq_gather_shifted_offset_z_u16.c | 21 + .../vldrhq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 15 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 15 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 15 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 17 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 17 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 17 + .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 13 + .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 21 + .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 21 + .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 21 + .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 21 + .../vldrwq_gather_shifted_offset_z_f32.c | 21 + .../vldrwq_gather_shifted_offset_z_s32.c | 21 + .../vldrwq_gather_shifted_offset_z_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 13 + .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 13 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f16.c | 21 + .../arm/mve/intrinsics/vminnmavq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u16.c | 22 + .../arm/mve/intrinsics/vmladavaq_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 21 + .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmladavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 21 + .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 21 + .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 22 + .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 21 + .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 21 + 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21 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 22 + 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.../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_s16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u16.c | 21 + .../arm/mve/intrinsics/vmullbq_int_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 21 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 22 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_p16.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_p8.c | 21 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 22 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 22 + .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_s16.c | 21 + .../arm/mve/intrinsics/vmulltq_int_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 21 + .../arm/mve/intrinsics/vmulltq_int_u16.c | 21 + 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+ .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 22 + .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 23 + 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21 + .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + 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.../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 15 + .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 21 + .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 23 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 15 + 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.../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 21 + .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 21 + .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 21 + .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 21 + .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 21 + .../vstrdq_scatter_shifted_offset_p_s64.c | 21 + .../vstrdq_scatter_shifted_offset_p_u64.c | 21 + .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 21 + .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 21 + .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 21 + .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 21 + .../vstrhq_scatter_shifted_offset_p_f16.c | 21 + .../vstrhq_scatter_shifted_offset_p_s16.c | 21 + .../vstrhq_scatter_shifted_offset_p_s32.c | 21 + .../vstrhq_scatter_shifted_offset_p_u16.c | 21 + .../vstrhq_scatter_shifted_offset_p_u32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 21 + .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 21 + .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 21 + .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 21 + .../vstrwq_scatter_shifted_offset_p_f32.c | 21 + .../vstrwq_scatter_shifted_offset_p_s32.c | 21 + .../vstrwq_scatter_shifted_offset_p_u32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 21 + .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 21 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 23 + 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gcc/testsuite/gcc.target/arm/vnmul-4.c | 4 +- gcc/testsuite/gcc.target/i386/avx512f-pr94300.c | 21 + gcc/testsuite/gcc.target/i386/avx512f-pr94343.c | 12 + gcc/testsuite/gcc.target/i386/avx512vl-pr93069.c | 12 + gcc/testsuite/gcc.target/i386/avx512vl-pr94343.c | 12 + gcc/testsuite/gcc.target/i386/pr57193.c | 3 +- gcc/testsuite/gcc.target/i386/pr81213-2.c | 12 + gcc/testsuite/gcc.target/i386/pr81213.c | 12 +- gcc/testsuite/gcc.target/i386/pr94283.c | 5 + gcc/testsuite/gcc.target/i386/pr94308.c | 31 + gcc/testsuite/gcc.target/powerpc/bswap64-4.c | 6 +- gcc/testsuite/gcc.target/powerpc/pragma_misc9.c | 47 + gcc/testsuite/gcc.target/powerpc/pragma_power6.c | 17 + gcc/testsuite/gcc.target/powerpc/pragma_power7.c | 32 + gcc/testsuite/gcc.target/powerpc/pragma_power8.c | 52 + gcc/testsuite/gcc.target/powerpc/pragma_power9.c | 63 + .../gcc.target/powerpc/vsu/vec-all-nez-7.c | 3 +- .../gcc.target/powerpc/vsu/vec-any-eqz-7.c | 3 +- gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr90136a.d | 21 + gcc/testsuite/gdc.dg/pr90136b.d | 21 + gcc/testsuite/gdc.dg/pr90136c.d | 9 + gcc/testsuite/gdc.dg/pr92216.d | 4 +- gcc/testsuite/gdc.dg/pr93038.d | 10 + gcc/testsuite/gdc.dg/pr93038b.d | 11 + gcc/testsuite/gdc.dg/pr94424.d | 19 + gcc/testsuite/gdc.test/compilable/compilable.exp | 30 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + .../gdc.test/fail_compilation/fail_compilation.exp | 30 + gcc/testsuite/gdc.test/gdc-test.exp | 469 - gcc/testsuite/gdc.test/runnable/runnable.exp | 35 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- .../gdc.test/{runnable => runnable_cxx}/cabi1.d | 0 .../{runnable => runnable_cxx}/cpp_abi_tests.d | 0 .../gdc.test/{runnable => runnable_cxx}/cppa.d | 0 .../{runnable => runnable_cxx}/externmangle.d | 0 .../{runnable => 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gcc/testsuite/gfortran.dg/pr94030_1.f90 | 11 + gcc/testsuite/gfortran.dg/pr94030_2.f90 | 33 + gcc/testsuite/gfortran.dg/pr94285.f90 | 5 + gcc/testsuite/gfortran.dg/pr94329.f90 | 12 + gcc/testsuite/gfortran.dg/select_rank_4.f90 | 26 + .../gfortran.dg/unlimited_polymorphic_31.f03 | 3 + gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 +- gcc/testsuite/jit.dg/all-non-failing-tests.h | 30 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/jit.dg/test-version.c | 26 + gcc/testsuite/lib/gdc-utils.exp | 475 + gcc/testsuite/lib/gdc.exp | 106 +- gcc/testsuite/lib/target-supports.exp | 65 +- gcc/tree-if-conv.c | 24 +- gcc/tree-object-size.c | 5 +- gcc/tree-sra.c | 37 +- gcc/tree-ssa-dom.c | 9 +- gcc/tree-ssa-forwprop.c | 60 +- gcc/tree-ssa-loop-im.c | 3 +- gcc/tree-ssa-loop-manip.c | 12 +- gcc/tree-ssa-math-opts.c | 6 +- gcc/tree-ssa-phiopt.c | 10 +- gcc/tree-ssa-propagate.c | 19 +- gcc/tree-ssa-reassoc.c | 14 +- gcc/tree-ssa-sccvn.c | 2 + gcc/tree-ssa-strlen.c | 19 +- gcc/tree-ssa-strlen.h | 2 +- gcc/tree-vect-loop.c | 50 +- gcc/tree-vect-slp.c | 58 +- gcc/tree-vect-stmts.c | 210 +- gcc/tree.c | 42 + gcc/var-tracking.c | 27 +- gcc/varasm.c | 20 + include/ChangeLog | 29 + include/lto-symtab.h | 13 + include/plugin-api.h | 93 +- libcpp/po/ChangeLog | 4 + libcpp/po/sr.po | 78 +- libgcc/ChangeLog | 9 + libgcc/config/arm/lib1funcs.S | 33 +- libgomp/ChangeLog | 38 + libgomp/target.c | 18 +- libgomp/testsuite/libgomp.c++/pr93931.C | 120 + .../libgomp.c-c++-common/function-not-offloaded.c | 1 + libgomp/testsuite/libgomp.c/target-link-1.c | 3 - .../libgomp.fortran/target-enter-data-1.f90 | 36 + .../libgomp.oacc-c++/firstprivate-mappings-1.C | 9 + .../firstprivate-mappings-1.c | 9 + .../libgomp.oacc-fortran/atomic_capture-1.f90 | 30 +- libstdc++-v3/ChangeLog | 246 + libstdc++-v3/doc/html/manual/appendix_free.html | 2 +- libstdc++-v3/doc/xml/manual/appendix_free.xml | 2 +- libstdc++-v3/include/bits/fs_fwd.h | 42 - libstdc++-v3/include/bits/fs_path.h | 11 +- libstdc++-v3/include/bits/iterator_concepts.h | 50 + libstdc++-v3/include/bits/range_access.h | 27 +- libstdc++-v3/include/bits/range_cmp.h | 3 + libstdc++-v3/include/bits/stl_algobase.h | 2 +- libstdc++-v3/include/bits/stl_iterator.h | 276 +- .../include/bits/stl_iterator_base_types.h | 4 +- libstdc++-v3/include/bits/stream_iterator.h | 4 +- libstdc++-v3/include/bits/streambuf_iterator.h | 4 +- libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- libstdc++-v3/include/experimental/executor | 226 +- libstdc++-v3/include/experimental/socket | 18 +- libstdc++-v3/include/std/chrono | 206 +- libstdc++-v3/include/std/concepts | 2 +- libstdc++-v3/include/std/condition_variable | 3 + libstdc++-v3/include/std/future | 3 + libstdc++-v3/include/std/mutex | 3 + libstdc++-v3/include/std/shared_mutex | 6 + libstdc++-v3/include/std/stop_token | 12 + libstdc++-v3/include/std/thread | 3 + libstdc++-v3/include/std/type_traits | 80 +- libstdc++-v3/include/std/version | 7 +- .../allocator_traits/members/92878_92947.cc | 51 + .../testsuite/20_util/any/assign/92878_92947.cc | 46 + .../testsuite/20_util/any/cons/92878_92947.cc | 46 + .../20_util/is_constructible/92878_92947.cc | 49 + .../testsuite/20_util/is_constructible/value-2.cc | 4 + .../20_util/is_nothrow_constructible/94003.cc | 46 + .../20_util/optional/assignment/92878_92947.cc | 47 + .../testsuite/20_util/optional/cons/92878_92947.cc | 46 + .../testsuite/20_util/pair/cons/92878_92947.cc | 49 + .../20_util/shared_ptr/creation/92878_92947.cc | 46 + .../construct_at/92878_92947.cc | 50 + .../testsuite/20_util/time_point/cons/81468.cc | 8 +- .../time_point/requirements/duration_neg.cc | 32 + .../20_util/unique_ptr/creation/92878_92947.cc | 46 + .../20_util/uses_allocator/92878_92947.cc | 67 + .../testsuite/20_util/variant/92878_92947.cc | 91 + .../deque/modifiers/emplace/92878_92947.cc | 62 + .../forward_list/modifiers/92878_92947.cc | 62 + .../list/modifiers/emplace/92878_92947.cc | 78 + .../map/modifiers/emplace/92878_92947.cc | 137 + .../multimap/modifiers/emplace/92878_92947.cc | 71 + .../multiset/modifiers/emplace/92878_92947.cc | 70 + .../23_containers/priority_queue/92878_92947.cc | 52 + .../testsuite/23_containers/queue/92878_92947.cc | 47 + .../set/modifiers/emplace/92878_92947.cc | 70 + .../testsuite/23_containers/stack/92878_92947.cc | 47 + .../unordered_map/modifiers/92878_92947.cc | 137 + .../unordered_multimap/modifiers/92878_92947.cc | 71 + .../unordered_multiset/modifiers/92878_92947.cc | 78 + .../unordered_set/modifiers/92878_92947.cc | 78 + .../vector/modifiers/emplace/92878_92947.cc | 61 + .../24_iterators/back_insert_iterator/constexpr.cc | 54 + .../front_insert_iterator/constexpr.cc | 54 + .../headers/iterator/synopsis_c++17.cc | 18 + .../24_iterators/insert_iterator/constexpr.cc | 57 + .../24_iterators/move_iterator/greedy_ops.cc | 8 +- .../24_iterators/move_iterator/input_iterator.cc | 42 + .../24_iterators/move_iterator/move_only.cc | 61 + .../24_iterators/move_iterator/rel_ops_c++20.cc | 163 + .../24_iterators/reverse_iterator/greedy_ops.cc | 8 +- .../24_iterators/reverse_iterator/rel_ops_c++20.cc | 193 + .../27_io/filesystem/path/generic/94242.cc | 52 + .../filesystem/path/generic/generic_string.cc | 32 + .../30_threads/condition_variable/members/2.cc | 2 + .../condition_variable/members/clock_neg.cc | 61 + .../condition_variable_any/members/clock_neg.cc | 61 + .../30_threads/future/members/clock_neg.cc | 59 + .../recursive_timed_mutex/try_lock_until/3.cc | 2 +- .../try_lock_until/clock_neg.cc | 57 + .../30_threads/shared_future/members/clock_neg.cc | 59 + .../30_threads/shared_lock/locking/clock_neg.cc | 59 + .../shared_timed_mutex/try_lock_until/1.cc | 87 + .../shared_timed_mutex/try_lock_until/2.cc | 74 + .../shared_timed_mutex/try_lock_until/clock_neg.cc | 57 + .../30_threads/timed_mutex/try_lock_until/3.cc | 2 +- .../30_threads/timed_mutex/try_lock_until/4.cc | 2 +- .../timed_mutex/try_lock_until/clock_neg.cc | 57 + .../30_threads/unique_lock/locking/clock_neg.cc | 59 + .../filesystem/path/generic/generic_string.cc | 46 +- .../net/execution_context/use_service.cc | 6 +- .../testsuite/experimental/net/executor/1.cc | 93 + .../std/ranges/headers/ranges/synopsis.cc | 6 + .../testsuite/std/time/clock/file/members.cc | 39 + .../testsuite/std/time/clock/file/overview.cc | 43 + libstdc++-v3/testsuite/std/time/syn_c++20.cc | 199 + libstdc++-v3/testsuite/std/time/traits/is_clock.cc | 141 + libstdc++-v3/testsuite/util/slow_clock.h | 3 + lto-plugin/ChangeLog | 20 + lto-plugin/lto-plugin.c | 141 +- 3003 files changed, 303060 insertions(+), 146532 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/attr-copy.c create mode 100644 gcc/testsuite/c-c++-common/pr94385.c create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/abi/lambda-vis.C create mode 100644 gcc/testsuite/g++.dg/abi/mangle74.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic5.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic7.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic8.C create mode 100644 gcc/testsuite/g++.dg/concepts/pr94252.C create mode 100644 gcc/testsuite/g++.dg/conversion/op7.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/exceptions-test-01-n4849-a.C create mode 100644 gcc/testsuite/g++.dg/coroutines/torture/symmetric-transfer-00-basic.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/enum40.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl1.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/alias-decl3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-nsdmi2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C create mode 100644 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gcc/testsuite/g++.dg/warn/Wmismatched-tags-6.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-6.C create mode 100644 gcc/testsuite/g++.dg/warn/Wredundant-tags-7.C create mode 100644 gcc/testsuite/g++.target/aarch64/pr94052.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94144.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94238.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94412.c create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/Walloca-larger-than-3.c create mode 100644 gcc/testsuite/gcc.dg/Walloca-larger-than-3.h create mode 100644 gcc/testsuite/gcc.dg/Wvla-larger-than-4.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-1.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-2.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/compound-assignment-3.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/malloc-5.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94047.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/attr-weakref-5.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-1.c create mode 100644 gcc/testsuite/gcc.dg/debug/dwarf2/pr93751-2.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94271_0.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94271_1.c create mode 100644 gcc/testsuite/gcc.dg/pr84131.c create mode 100644 gcc/testsuite/gcc.dg/pr93573-1.c create mode 100644 gcc/testsuite/gcc.dg/pr93573-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94172-2.c create mode 100644 gcc/testsuite/gcc.dg/pr94188.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.dg/pr94269.c create mode 100644 gcc/testsuite/gcc.dg/pr94277.c create mode 100644 gcc/testsuite/gcc.dg/pr94283.c create mode 100644 gcc/testsuite/gcc.dg/pr94286.c create mode 100644 gcc/testsuite/gcc.dg/pr94292.c create mode 100644 gcc/testsuite/gcc.dg/pr94344.c create mode 100644 gcc/testsuite/gcc.dg/pr94368.c create mode 100644 gcc/testsuite/gcc.dg/pr94436.c create mode 100644 gcc/testsuite/gcc.dg/sms-compare-debug-1.c create mode 100644 gcc/testsuite/gcc.dg/sms-compare-debug-2.c create mode 100644 gcc/testsuite/gcc.dg/torture/pr94206.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93435.c create mode 100644 gcc/testsuite/gcc.dg/ubsan/pr94423.c create mode 100644 gcc/testsuite/gcc.dg/vect/pr93069.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94201.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94398.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94435.c create mode 100644 gcc/testsuite/gcc.target/arm/cmp-3.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/asrl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/lsll.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqshll.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshl.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvaq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_f32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmlaq_rot90_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_m_s16_f16.c create mode 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlaldavq_p_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovntq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_m_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c create 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlashq_n_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshrntq_m_n_s16.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshlq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqsubq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlaldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhaxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmlsldavhxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_u16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlcq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_m_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_u16.c 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