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from dead081 Bitcode: Change module reader functions to return an llvm::Expected. new 9027123 [AMDGPU] Add f16 support (VI+)

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Summary of changes: lib/Target/AMDGPU/AMDGPU.td | 6 + lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 56 +- lib/Target/AMDGPU/AMDGPUInstructions.td | 1 + lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 2 + lib/Target/AMDGPU/AMDGPUSubtarget.h | 4 + lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 35 +- lib/Target/AMDGPU/SIFoldOperands.cpp | 16 +- lib/Target/AMDGPU/SIISelLowering.cpp | 116 +++- lib/Target/AMDGPU/SIISelLowering.h | 16 + lib/Target/AMDGPU/SIInstrInfo.cpp | 29 +- lib/Target/AMDGPU/SIInstrInfo.td | 13 +- lib/Target/AMDGPU/SIInstructions.td | 61 +- lib/Target/AMDGPU/SIRegisterInfo.td | 12 +- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 1 + lib/Target/AMDGPU/VOP1Instructions.td | 36 +- lib/Target/AMDGPU/VOP2Instructions.td | 59 +- lib/Target/AMDGPU/VOP3Instructions.td | 22 +- lib/Target/AMDGPU/VOPCInstructions.td | 370 +++++++---- test/CodeGen/AMDGPU/fadd.f16.ll | 150 +++++ test/CodeGen/AMDGPU/fcmp.f16.ll | 744 ++++++++++++++++++++++ test/CodeGen/AMDGPU/fdiv.f16.ll | 31 + test/CodeGen/AMDGPU/fmul.f16.ll | 150 +++++ test/CodeGen/AMDGPU/fp_to_sint.ll | 10 +- test/CodeGen/AMDGPU/fp_to_uint.ll | 10 +- test/CodeGen/AMDGPU/fpext.f16.ll | 70 ++ test/CodeGen/AMDGPU/fptosi.f16.ll | 112 ++++ test/CodeGen/AMDGPU/fptoui.f16.ll | 113 ++++ test/CodeGen/AMDGPU/fptrunc.f16.ll | 72 +++ test/CodeGen/AMDGPU/fsub.f16.ll | 150 +++++ test/CodeGen/AMDGPU/half.ll | 30 +- test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll | 155 +++++ test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll | 129 ++++ test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll | 45 ++ test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll | 18 + test/CodeGen/AMDGPU/llvm.ceil.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.cos.f16.ll | 55 ++ test/CodeGen/AMDGPU/llvm.exp2.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.floor.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.fma.f16.ll | 235 +++++++ test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 116 ++++ test/CodeGen/AMDGPU/llvm.log2.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.maxnum.f16.ll | 153 +++++ test/CodeGen/AMDGPU/llvm.minnum.f16.ll | 153 +++++ test/CodeGen/AMDGPU/llvm.rint.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.sin.f16.ll | 55 ++ test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 49 ++ test/CodeGen/AMDGPU/llvm.trunc.f16.ll | 49 ++ test/CodeGen/AMDGPU/sint_to_fp.i64.ll | 62 +- test/CodeGen/AMDGPU/sitofp.f16.ll | 87 +++ test/CodeGen/AMDGPU/uint_to_fp.i64.ll | 57 +- test/CodeGen/AMDGPU/uitofp.f16.ll | 87 +++ test/CodeGen/AMDGPU/v_mac_f16.ll | 608 ++++++++++++++++++ test/CodeGen/AMDGPU/v_madak_f16.ll | 50 ++ test/MC/Disassembler/AMDGPU/sdwa_vi.txt | 4 +- 60 files changed, 4741 insertions(+), 276 deletions(-) create mode 100644 test/CodeGen/AMDGPU/fadd.f16.ll create mode 100644 test/CodeGen/AMDGPU/fcmp.f16.ll create mode 100644 test/CodeGen/AMDGPU/fdiv.f16.ll create mode 100644 test/CodeGen/AMDGPU/fmul.f16.ll create mode 100644 test/CodeGen/AMDGPU/fpext.f16.ll create mode 100644 test/CodeGen/AMDGPU/fptosi.f16.ll create mode 100644 test/CodeGen/AMDGPU/fptoui.f16.ll create mode 100644 test/CodeGen/AMDGPU/fptrunc.f16.ll create mode 100644 test/CodeGen/AMDGPU/fsub.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cos.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.fract.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rcp.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.sin.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.ceil.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.cos.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.exp2.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.floor.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.fma.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.log2.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.maxnum.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.minnum.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.rint.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.sin.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.sqrt.f16.ll create mode 100644 test/CodeGen/AMDGPU/llvm.trunc.f16.ll create mode 100644 test/CodeGen/AMDGPU/sitofp.f16.ll create mode 100644 test/CodeGen/AMDGPU/uitofp.f16.ll create mode 100644 test/CodeGen/AMDGPU/v_mac_f16.ll create mode 100644 test/CodeGen/AMDGPU/v_madak_f16.ll