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from 5b880f8d07b [Mips] Return true in enableMultipleCopyHints(). new 0c0db7175b6 Mark MergedLoadStoreMotion as not preserving MemDep results new d9086c893cc StructurizeCFG: Test for branch divergence correctly new 02e435715e5 AMDGPU: Track physreg uses in SILoadStoreOptimizer new c34350228ef TableGen: Add !size operation new 01724121ace TableGen: Fix typeIsConvertibleTo for record types new 69ccda272dd TableGen: BitInit and VarBitInit are typed new c374065b04c TableGen: Avoid using resolveListElementReference in TGParser
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Summary of changes: docs/TableGen/LangIntro.rst | 3 + docs/TableGen/LangRef.rst | 2 +- include/llvm/Analysis/DivergenceAnalysis.h | 8 +- include/llvm/TableGen/Record.h | 28 +++-- lib/TableGen/Record.cpp | 20 +++- lib/TableGen/TGLexer.cpp | 1 + lib/TableGen/TGLexer.h | 2 +- lib/TableGen/TGParser.cpp | 31 +++--- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp | 64 ++++++------ lib/Transforms/Scalar/MergedLoadStoreMotion.cpp | 49 ++------- lib/Transforms/Scalar/StructurizeCFG.cpp | 15 ++- test/CodeGen/AMDGPU/control-flow-optnone.ll | 4 +- test/CodeGen/AMDGPU/ds_read2.ll | 23 ++++ test/CodeGen/AMDGPU/merge-load-store-physreg.mir | 116 +++++++++++++++++++++ test/CodeGen/AMDGPU/smrd.ll | 29 ++++-- test/TableGen/if-type.td | 11 ++ test/TableGen/if.td | 26 ++++- test/TableGen/size.td | 34 ++++++ test/Transforms/GVN/pr36063.ll | 22 ++++ .../StructurizeCFG/AMDGPU/uniform-regions.ll | 82 +++++++++++++++ 20 files changed, 453 insertions(+), 117 deletions(-) create mode 100644 test/CodeGen/AMDGPU/merge-load-store-physreg.mir create mode 100644 test/TableGen/if-type.td create mode 100644 test/TableGen/size.td create mode 100644 test/Transforms/GVN/pr36063.ll create mode 100644 test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll