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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-check_binutils in repository toolchain/ci/binutils-gdb.

from b763d508db x86/Intel: correct AVX512 S/G disassembly adds 7056f312d0 Use bool for "parse_completion" adds 0b9f3e5463 Automatic date update in version.in adds ebdcad3fdd RISC-V: Improve multiple relax passes problem. adds da944c8a70 x86: remove stray uses of xmmq_mode adds ac7a231133 x86: drop a few redundant EVEX-related checks adds fd1fd06186 x86: re-order logic in OP_XMM() adds 1e1e17e5e2 Automatic date update in version.in adds 68cb21837f PE image base fallout adds 78c84bf926 Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)

No new revisions were added by this update.

Summary of changes: bfd/ChangeLog | 16 ++++++ bfd/elfnn-riscv.c | 48 ++++++++++++++---- bfd/elfxx-riscv.h | 6 +++ bfd/version.h | 2 +- gdb/ChangeLog | 11 ++++ gdb/ada-lang.c | 10 ++-- gdb/ada-lang.h | 12 ++--- gdb/parser-defs.h | 4 +- ld/ChangeLog | 20 ++++++++ ld/emultempl/riscvelf.em | 6 ++- ld/testsuite/ld-gc/gc.exp | 31 ++++++++---- ld/testsuite/ld-gc/pr13683.d | 1 + ld/testsuite/ld-gc/pr14265.d | 15 +++--- ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 1 + ld/testsuite/ld-riscv-elf/restart-relax.d | 14 ++++++ ld/testsuite/ld-riscv-elf/restart-relax.s | 17 +++++++ ld/testsuite/ld-scripts/crossref.exp | 6 ++- ld/testsuite/ld-srec/srec.exp | 9 ++-- ld/testsuite/lib/ld-lib.exp | 2 +- opcodes/ChangeLog | 20 ++++++++ opcodes/i386-dis.c | 80 ++++++++++++++---------------- 21 files changed, 242 insertions(+), 89 deletions(-) create mode 100644 ld/testsuite/ld-riscv-elf/restart-relax.d create mode 100644 ld/testsuite/ld-riscv-elf/restart-relax.s