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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allnoconfig in repository toolchain/ci/llvm-project.

from b409f73e1fd [ARM][TypePromotion] Re-enable by default adds c7dc4734d23 [llvm-exegesis] Check counters before running adds f5b7dd3c9ec [mlir][Linalg] Delete unused LinalgLibraryOps.td adds 27a0795943f [InstCombine] Fix infinite loop due to bitcast <-> phi transforms adds 108645cd0ad [InstCombine] add tests for masked bit set/clear; NFC adds e6bdecf1cd6 [AArch64] add test for fsub+fneg; NFC adds ff429c5eaf7 [OpenCL] Remove redundant foreach in OpenCLBuiltins.td; NFC adds fcbf05bbdcc [PowerPC][NFC] Fix clang-tidy warning adds 7adb5c2aca8 Revert "[InstCombine] Fix infinite loop due to bitcast <-> [...] adds df3b56c9054 [Attributor][Fix] Avoid leaking memory after D68765 adds d89c4cb9380 Match code following lambdas when ignoring invisible nodes adds 06fdbf3dafb Unnest struct in Matcher implementation adds 69bb99914f3 Implement additional traverse() overloads adds eb5c026ef0b [InstCombine] add/adjust tests for masked bit; NFC adds a041c4ec6f7 [InstCombine] fold zext of masked bit set/clear adds 430bba2a0f3 [mlir] Make code blocks more consistent adds 5e5a1d27909 [CodeGen] Emit conj/conjf/confjl libcalls as fneg instructi [...] adds 73855e43009 [X86] Add test case for opposite branch condition for PR44412. NFC adds 7544cb8807b [mlir][docs] Remove redundant path prefix adds 8be5a0fe12b [OPENMP]Emit artificial threprivate vars as threadlocal, if [...] adds 79d401905fc [amdgpu] Fix scoreboard updating on `s_waitcnt_vscnt`. adds b65ca8e5db6 Revert "[Diagnostic] Add ftabstop to -Wmisleading-indentation" adds 64cf26548a4 AMDGPU: Precommit test showing extra instructions are introduced adds 4ae3120ed81 [LegalizeVectorOps][AArch64] Stop asking for v4f16 fp_round [...] adds 1cc8a74de34 [X86] Use carry flag from add for (seteq (add X, -1), -1). adds 374e0299cf0 [X86][InstCombine] Add constant folding and simplification [...] adds 26bdc603f76 [X86] Constant fold KSHIFT of an all zeros vector to just a [...] adds e3e13db714e [ELF][RISCV] Improve error message for unknown relocations adds 4d7201e7b98 DAG: Stop trying to fold FP -(x-y) -> y-x in getNode with nsz adds 468a0cb5f39 [X86] Add X87 FCMOV support to X86FlagsCopyLowering. adds 86f48999f46 [X86] Fix typo in getCMovOpcode. adds e9963034314 [Attributor] AAValueConstantRange: Value range analysis usi [...] adds 47e3d3ec0c5 [ELF][RISCV][test] Test absolute/PC-relative/branch relocat [...] adds d2bb8c16e71 [MC][TargetMachine] Delete MCTargetOptions::MCPIECopyRelocations

No new revisions were added by this update.

Summary of changes: clang/include/clang/ASTMatchers/ASTMatchers.h | 46 ++ .../clang/ASTMatchers/ASTMatchersInternal.h | 59 +- clang/lib/ASTMatchers/ASTMatchFinder.cpp | 2 +- clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGBuiltin.cpp | 5 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 9 +- clang/lib/Parse/ParseStmt.cpp | 41 +- clang/lib/Sema/OpenCLBuiltins.td | 108 ++-- clang/test/CodeGen/complex-libcalls-2.c | 20 + clang/test/CodeGen/complex-libcalls.c | 12 +- .../OpenMP/master_taskloop_reduction_codegen.cpp | 4 +- .../master_taskloop_simd_reduction_codegen.cpp | 4 +- .../parallel_master_taskloop_reduction_codegen.cpp | 4 +- ...llel_master_taskloop_simd_reduction_codegen.cpp | 4 +- clang/test/OpenMP/taskloop_reduction_codegen.cpp | 23 +- .../OpenMP/taskloop_simd_reduction_codegen.cpp | 4 +- clang/test/Parser/warn-misleading-indentation.cpp | 83 +-- .../ASTMatchers/ASTMatchersTraversalTest.cpp | 92 +++ lld/ELF/Arch/RISCV.cpp | 31 +- lld/test/ELF/riscv-undefined-weak.s | 79 +++ llvm/include/llvm/MC/MCTargetOptions.h | 1 - .../llvm/MC/MCTargetOptionsCommandFlags.inc | 3 - llvm/include/llvm/Transforms/IPO/Attributor.h | 167 +++++- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 + .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 5 + llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 - llvm/lib/MC/MCTargetOptions.cpp | 4 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 - llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 +- llvm/lib/Target/TargetMachine.cpp | 15 +- llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 73 +++ llvm/lib/Target/X86/X86ISelLowering.cpp | 44 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +- llvm/lib/Transforms/IPO/Attributor.cpp | 506 ++++++++++++++++- .../Transforms/InstCombine/InstCombineCalls.cpp | 58 ++ .../Transforms/InstCombine/InstCombineCasts.cpp | 20 +- llvm/test/CodeGen/AArch64/arm64-fp.ll | 15 + .../fneg-fold-legalize-dag-increase-insts.ll | 24 + llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir | 17 + .../CodeGen/X86/global-access-pie-copyrelocs.ll | 151 ----- llvm/test/CodeGen/X86/masked_store.ll | 12 - llvm/test/CodeGen/X86/pr44396.ll | 47 ++ llvm/test/CodeGen/X86/pr44412.ll | 38 +- .../Attributor/IPConstantProp/return-constant.ll | 6 +- ...lve-after-each-resolving-undefs-for-function.ll | 7 +- .../Transforms/Attributor/dereferenceable-1.ll | 105 +++- .../Attributor/lvi-after-jumpthreading.ll | 181 ++++++ llvm/test/Transforms/Attributor/lvi-for-ashr.ll | 46 ++ llvm/test/Transforms/Attributor/range.ll | 446 +++++++++++++++ llvm/test/Transforms/Attributor/value-simplify.ll | 37 +- .../test/Transforms/InstCombine/X86/x86-bmi-tbm.ll | 132 +++++ llvm/test/Transforms/InstCombine/zext.ll | 277 ++++++++- llvm/tools/llvm-exegesis/lib/Latency.cpp | 2 - llvm/tools/llvm-exegesis/lib/Target.cpp | 11 + llvm/tools/llvm-exegesis/llvm-exegesis.cpp | 13 +- mlir/docs/ConversionToLLVMDialect.md | 2 +- mlir/docs/DeclarativeRewrites.md | 42 +- mlir/docs/RationaleSimplifiedPolyhedralForm.md | 12 +- mlir/docs/Tutorials/Toy/Ch-1.md | 4 +- mlir/docs/Tutorials/Toy/Ch-2.md | 4 +- mlir/docs/Tutorials/Toy/Ch-3.md | 12 +- mlir/docs/Tutorials/Toy/Ch-4.md | 2 +- mlir/docs/Tutorials/Toy/Ch-5.md | 2 +- mlir/docs/Tutorials/Toy/Ch-6.md | 7 +- .../mlir/Dialect/Linalg/IR/LinalgLibraryOps.td | 616 --------------------- mlir/lib/Support/CMakeLists.txt | 2 +- 67 files changed, 2629 insertions(+), 1203 deletions(-) create mode 100644 clang/test/CodeGen/complex-libcalls-2.c create mode 100644 lld/test/ELF/riscv-undefined-weak.s create mode 100644 llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll create mode 100644 llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir delete mode 100644 llvm/test/CodeGen/X86/global-access-pie-copyrelocs.ll create mode 100644 llvm/test/CodeGen/X86/pr44396.ll create mode 100644 llvm/test/Transforms/Attributor/lvi-after-jumpthreading.ll create mode 100644 llvm/test/Transforms/Attributor/lvi-for-ashr.ll create mode 100644 llvm/test/Transforms/Attributor/range.ll delete mode 100644 mlir/include/mlir/Dialect/Linalg/IR/LinalgLibraryOps.td