This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch master in repository gcc.

from f6da8c5b993 LoongArch: doc: Put the '-mtls-dialect=opt' option descript [...] new 28751389a68 RISC-V: Fix wrong LMUL when only implict zve32f.

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: gcc/config/riscv/riscv-v.cc | 8 +- gcc/config/riscv/riscv-vector-builtins-types.def | 322 ++++++++++----------- gcc/config/riscv/riscv-vector-switch.def | 84 +++--- gcc/config/riscv/vector-iterators.md | 256 ++++++++-------- .../gcc.target/riscv/rvv/autovec/pr111391-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/abi-14.c | 84 +++--- gcc/testsuite/gcc.target/riscv/rvv/base/abi-16.c | 98 +++---- gcc/testsuite/gcc.target/riscv/rvv/base/abi-18.c | 112 +++---- .../riscv/rvv/base/vsetvl_zve32-1.c} | 8 +- .../gcc.target/riscv/rvv/base/vsetvl_zve32-2.c | 25 ++ 10 files changed, 514 insertions(+), 485 deletions(-) copy gcc/testsuite/{gcc.dg/tree-ssa/pr80898-2.c => gcc.target/riscv/rvv/base/vsetv [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl_zve32-2.c