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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-arm-build_cross in repository toolchain/ci/binutils-gdb.

from 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0

No new revisions were added by this update.

Summary of changes: bfd/ChangeLog | 30 + bfd/elf.c | 5 +- bfd/elf32-bfin.c | 235 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 13 + binutils/MAINTAINERS | 6 +- binutils/po/sv.po | 3804 +++++++++++--------- binutils/readelf.c | 6 +- gas/ChangeLog | 40 + gas/Makefile.am | 4 +- gas/Makefile.in | 4 +- gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 51 + gdb/MAINTAINERS | 1 + gdb/objfiles.h | 3 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/remote.c | 330 +- gdb/testsuite/ChangeLog | 17 + gdb/testsuite/gdb.base/style.exp | 49 +- gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- .../gdb.server/stop-reply-no-thread-multi.c | 77 + .../gdb.server/stop-reply-no-thread-multi.exp | 136 + gdb/trad-frame.c | 5 +- gdb/tui/tui.c | 4 +- gold/ChangeLog | 4 + gold/po/fr.po | 730 ++-- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 17 + ld/po/fr.po | 3699 ++++++++++--------- ld/testsuite/config/default.exp | 5 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++---- sim/ChangeLog | 7 + sim/common/ChangeLog | 6 + sim/common/sim-watch.c | 13 +- sim/configure | 16 +- sim/configure.ac | 16 +- sim/h8300/ChangeLog | 14 +- sim/h8300/compile.c | 91 +- sim/h8300/sim-main.h | 1 - sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 ----------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 - sim/testsuite/d10v-elf/configure | 2984 --------------- sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 --------------- sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 --------------- sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 --------------- sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 152 files changed, 7204 insertions(+), 21919 deletions(-) create mode 100644 gdb/testsuite/gdb.server/stop-reply-no-thread-multi.c create mode 100644 gdb/testsuite/gdb.server/stop-reply-no-thread-multi.exp delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%)