This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-defconfig in repository toolchain/ci/llvm-project.

from 586952f4cef Optimize std::midpoint for integers adds fff2721286e [BPF] Fix CO-RE bugs with bitfields adds 4264e7bbfdb [CUDA][HIP] Disable emitting llvm.linker.options in device [...] adds 0aba69eb1a0 [analyzer] Add test directory for scan-build. adds 31be9f3f7de Fix clone_constant_impl to correctly deal with null pointers adds 48223d92a98 [analyzer] Fixup scan-build tests for non-Darwin platforms. adds abc04ff4012 [analyzer] Require darwin for scan-build tests adds f65493a83e3 [X86] Teach X86MCInstLower to swap operands of commutable i [...] adds 9f34447f3ff [BPF] fix a use after free bug adds 58acbce3def [IR] Add Freeze instruction adds 103968d147b [X86] Lower the cost of avx512 horizontal bool and/or reduc [...] adds 92ef101da91 [IR] Remove switch's default block that causes clang 8 raise error adds db5074dc102 [lldb][NFC] Give some parameters in CommandInterpreter more [...] adds edfb8eea575 [AArch64] Update test checks on merge-store-dependency.ll. NFC adds 92164cf25d5 Recommit "[HardwareLoops] Optimisation remarks" adds e578d0fd295 [mips] Fix `__mips_isa_rev` macros value for Octeon CPU adds 0d14656b9d8 [mips] Set __OCTEON__ macros adds b4c5b8f3f51 DWARFDebugLoclists: Make it possible to read relocated addresses adds 0d47c7aba36 [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook adds ccf1a5f4bbe [InstCombine] dropRedundantMaskingOfLeftShiftInput(): trunc [...] adds 12c4a71ca9d [LoopUnroll] peel-loop-conditions.ll: add some 'is even/odd [...] adds 28cf9698abd MemoryRegion: Print "don't know" permission values as such adds 4ecff91ed1d lldb/minidump: Add support for the alternate ARM64 constant adds 9a8d477a0e0 [OpenCL] Add builtin function attribute handling adds 0e56b0f94bf [OpenCL] Group builtin functions by prototype adds 9357b5d0849 Revert and patch "[Python] Remove readline module" adds f71e35dc1f3 lldb/breakpad: add suppport for the "x86_64h" architecture adds 7d9af03ff7a [Scheduling][ARM] Consistently enable PostRA Machine scheduling adds cf581d7977c [ARM] Always enable UseAA in the arm backend adds 646896a4422 Fix PR40644: miscompile indexed FP constant store adds 93767143147 [Clang FE] Recognize -mnop-mcount CL option (SystemZ only). adds 2d21068d9fa [Docs] Add LangRef documentation for freeze instruction adds f01b9aa89e8 [MachineScheduler] Enable AA in PostRA Machine scheduler adds 9f294fc4977 [AtomicExpandPass] Silence static analyzer warnings about o [...] adds d590498829d [lldb] Fix readline/libedit compat patch for py2 adds 3ce0c785018 [InstCombine] add tests for shift-logic-shift; NFC adds 1842fe6be3c Add missing GVN =operator. NFCI. adds 77debf51aba [GVN] Fix uninitialized variable warnings. NFCI. adds 0016c1f4004 [JumpThreading] Factor out common code to update the SSA fo [...] adds 68f39de042e [NFC][ObjC][ARC] Add tests for OptimizeRetainRVCall adds 47d1029788b [ObjC][ARC] Ignore lifetime markers between *ReturnValue calls adds 642916adc97 [OPENMP][DOCS]Fix coloring of the implemented features stat [...] adds c7f127d93f4 [MachineOutliner] Fix uninitialized variable warnings. NFCI. adds dec21e44514 [MCObjectFileInfo] Fix uninitialized variable warnings. NFCI. adds 95a25d88833 Fix uninitialized variable warning. NFCI. adds 100e797adb4 [LV] Apply sink-after & interleave-groups as VPlan transfor [...] adds 7b710a4294c [OPENMP]Improve diagnostics for unsupported unified addressing. adds 39525a67238 [DFAPacketizer] Allow up to 64 functional units adds df3ae1eb296 [lldb] [Python] Build readline override module only on Linux adds 03bf229bd44 [ARM] Multi-vector MVE spill test adds ade55d07871 [llvm-objcopy][ELF] Add OriginalType & OriginalFlags adds 5ad0103d8a0 [llvm-objcopy][ELF] Implement --only-keep-debug adds bc496677d0e [Object][MachO] Rewrite macho-invalid-fat-arch-size into YAML adds 7ad25836135 [MachineOutliner] Reduce scope of variable and stop duplica [...] adds 76166a1ac71 Use iterator prefix increment. NFCI. adds 117e6dd6cc2 Remove redundant assignment. NFCI. adds e64f7bfefe4 Revert "[Object][MachO] Rewrite macho-invalid-fat-arch-size [...] adds 893afb9ca14 [JumpThreading] Factor out code to merge basic blocks (NFC) adds 312932a3346 [globalisel][docs] Add KnownBits Analysis documentation adds 82588e05cc3 [SLP] - Add couple safety checks to TreeEntry::dump(). NFC adds 15140e4bacf [hip] Enable pointer argument lowering through coercing type. adds a9970036d43 [lldb] Fix Python 3 incompatibility in API/lit.cfg.py adds 87e0cb4f1ad [clangd] Implement semantic highlightings via findExplicitR [...] adds de56a890725 [AMDGPU] return Fail instead of SolfFail from addOperand() adds e74c5b96610 [globalisel] Rename G_GEP to G_PTR_ADD adds 00e53d912dd [X86] Specifically limit fmin/fmax commutativity to NoNaNs [...] adds 7035ea6e3e4 [dexter] Remove lit check for python 3 adds 63f49465c32 [dexter] Fix feature tests on Windows adds 3606b567849 ValueObject: Upstream early-exit from swift-lldb. (NFC) adds 4f12ba50bb2 [AMDGPU] Removed dead code handling M0CopyReg adds f1b4c4bfd0b [lit] Fix `not` calling internal commands adds 6cd47f9dd7d [llvm-objdump] Fix spurious "The end of the file was unexpe [...] adds 0a220de9e9c [HIP] Fix visibility for 'extern' device variables. adds 027aa27d95c [X86/Atomics] (Semantically) revert G246098, switch back to [...] adds f2e7679d0f0 [AMDGPU] Removed dead code from R600ISelLowering.cpp adds d77ef856fc2 Revert "[lit] Better/earlier errors when no tests are executed" adds 2ff545e76d1 Modernize add-dsym test Makefile adds 270fe47aae4 testsuite: skipIfNoSBHeaders should skip when running remotely adds 42beb8ed792 TestBatchMode.py: add missing @skipIfRemote adds 5f158d8e21b [X86] Gate select->fmin/fmax transform on NoSignedZeros ins [...] adds 2abcf44f4c9 [Reproducer] Add test case for expression evaluation adds de5417f81d4 [ValueObject] Upstream initialization from swift-lldb. adds 3ac6863efbb [ValueObject] Upstream early exit from swift-lldb. (NFC) adds 743461090a2 [Sema] Fixes templated friend member assertion adds a078c77d720 [MIR] Add MIR parsing for heap alloc site instruction markers adds dcec2ac4f35 [OPENMP50]Simplify processing of context selector scores. adds ee10d934ddd Fix typo so that '-O0' is correctly specified adds db036ee0a42 [X86/Atomics] Correct a few transforms for new atomic lowering adds 6a79e083a0d [lldb] Add a install target for lldb python on darwin adds 91ff598680e [Hexagon] getCompoundCandidateGroup - fix 'false' value is [...] adds 4b698645d30 [LoopRotationUtils] Check values are newly inserted into maps. adds 1e1ae46595b [CMake] Prevent adding lld to test dependency (TEST_DEPS) w [...] adds 37f4955c9ba [mips] Fix `getRegForInlineAsmConstraint` to do not crash o [...] adds dce53d71987 [IRMover] Use GlobalValue::getAddressSpace instead of direc [...] adds 39573daa76f Revert "[analyzer] Add test directory for scan-build." adds 40f3d1307cf [TestMTCSimple] Disable the test if you don't have libMTC adds 7effd37b00d [SLP] add tests for 2-wide reductions; NFC adds 521fc5e620b [AMDGPU] Add missing flags to DS_Real adds 7060840bc9c [globalisel][docs] Add a section about debugging with the b [...] adds 041f35c4680 [Automaton] Make Automaton thread-safe adds ad0dfb0a253 [globalisel][docs] Rework GMIR documentation and add an ear [...] adds e0dd8f36ce4 [globalisel][docs] Rework GMIR documentation and add an ear [...] adds b36e3a8bac3 [IRMover] Set Address Space for moved global values adds bcbb121ff6c Fixed a profdata file size detection on Windows system. adds 34688fafea8 Implement `sys::getHostCPUName()` for Darwin ARM adds 529bb8a9804 [PowerPC] Fix the incorrect 'RM' flag set on load/store instr

No new revisions were added by this update.

Summary of changes: clang-tools-extra/clangd/FindTarget.cpp | 4 + clang-tools-extra/clangd/FindTarget.h | 3 + clang-tools-extra/clangd/SemanticHighlighting.cpp | 248 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 9 + clang/docs/OpenMPSupport.rst | 10 +- clang/include/clang/Basic/Attr.td | 6 - clang/include/clang/Basic/CodeGenOptions.def | 1 + clang/include/clang/Basic/DiagnosticCommonKinds.td | 2 + clang/include/clang/Driver/Options.td | 2 + clang/lib/Basic/Targets/Mips.cpp | 5 +- clang/lib/CodeGen/CGCall.cpp | 9 + clang/lib/CodeGen/CGOpenMPRuntime.cpp | 38 +- clang/lib/CodeGen/CGOpenMPRuntimeNVPTX.cpp | 13 +- clang/lib/CodeGen/CodeGenFunction.cpp | 10 + clang/lib/CodeGen/CodeGenModule.cpp | 6 +- clang/lib/CodeGen/TargetInfo.cpp | 50 +- clang/lib/Driver/ToolChains/Clang.cpp | 16 +- clang/lib/Frontend/CompilerInvocation.cpp | 1 + clang/lib/Parse/ParseOpenMP.cpp | 7 +- clang/lib/Sema/OpenCLBuiltins.td | 97 +- clang/lib/Sema/SemaLookup.cpp | 12 +- clang/lib/Sema/SemaOpenMP.cpp | 6 +- clang/lib/Sema/SemaTemplate.cpp | 3 + .../test/CXX/temp/temp.spec/temp.expl.spec/p20.cpp | 11 +- clang/test/CodeGen/asm-goto.c | 6 +- clang/test/CodeGen/mnop-mcount.c | 26 + .../CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu | 69 + clang/test/CodeGenCUDA/amdgpu-visibility.cu | 10 + clang/test/CodeGenCUDA/ms-linker-options.cu | 19 + .../test/CodeGenOpenCL/fdeclare-opencl-builtins.cl | 22 + clang/test/Driver/hip-autolink.hip | 14 + clang/test/OpenMP/declare_variant_ast_print.c | 6 +- clang/test/OpenMP/declare_variant_ast_print.cpp | 48 +- clang/test/OpenMP/requires_codegen.cpp | 2 +- clang/test/Preprocessor/init.c | 10 + clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp | 158 +- compiler-rt/cmake/Modules/AddCompilerRT.cmake | 2 +- debuginfo-tests/CMakeLists.txt | 5 + debuginfo-tests/dexter/dex/builder/Builder.py | 4 +- .../dexter/dex/builder/scripts/windows/clang.bat | 2 +- debuginfo-tests/dexter/feature_tests/lit.local.cfg | 6 - lldb/CMakeLists.txt | 27 +- lldb/include/lldb/Interpreter/CommandInterpreter.h | 6 +- lldb/include/lldb/Target/MemoryRegionInfo.h | 18 +- lldb/packages/Python/lldbsuite/test/decorators.py | 3 + .../test/driver/batch_mode/TestBatchMode.py | 1 + .../functionalities/mtc/simple/TestMTCSimple.py | 6 +- .../postmortem/minidump-new/regions-linux-map.yaml | 2 +- .../Python/lldbsuite/test/macosx/add-dsym/Makefile | 24 +- lldb/source/Commands/CommandObjectMemory.cpp | 13 +- lldb/source/Core/Value.cpp | 11 +- lldb/source/Core/ValueObject.cpp | 14 + lldb/source/Interpreter/CommandInterpreter.cpp | 12 +- .../ObjectFile/Breakpad/BreakpadRecords.cpp | 2 +- .../Plugins/Process/minidump/MinidumpParser.cpp | 1 + .../ScriptInterpreter/Python/CMakeLists.txt | 1 + .../ScriptInterpreter/Python/PythonReadline.cpp | 88 + .../ScriptInterpreter/Python/PythonReadline.h | 26 + .../Python/ScriptInterpreterPython.cpp | 17 + lldb/source/Target/MemoryRegionInfo.cpp | 24 +- lldb/test/API/lit.cfg.py | 7 +- .../Shell/Minidump/memory-region-from-module.yaml | 3 +- .../Functionalities/Inputs/ExpressionEvaluation.in | 10 + .../Functionalities/TestExpressionEvaluation.test | 18 + .../Breakpad/Inputs/line-table-edgecases.syms | 2 +- llvm/docs/CommandGuide/llvm-objcopy.rst | 14 +- llvm/docs/GlobalISel/GMIR.rst | 207 +- llvm/docs/GlobalISel/GenericOpcode.rst | 674 +++++ llvm/docs/GlobalISel/KnownBits.rst | 100 + llvm/docs/GlobalISel/Pipeline.rst | 55 + llvm/docs/GlobalISel/block-extract.png | Bin 0 -> 88834 bytes llvm/docs/GlobalISel/index.rst | 2 + llvm/docs/LangRef.rst | 116 +- llvm/docs/MIRLangRef.rst | 4 + llvm/include/llvm-c/Core.h | 2 + llvm/include/llvm/Analysis/VectorUtils.h | 9 +- llvm/include/llvm/Bitcode/LLVMBitCodes.h | 3 +- llvm/include/llvm/CodeGen/DFAPacketizer.h | 45 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 4 +- .../include/llvm/CodeGen/GlobalISel/IRTranslator.h | 3 + .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 2 +- .../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 2 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 25 +- llvm/include/llvm/CodeGen/MachineOutliner.h | 12 +- llvm/include/llvm/CodeGen/TargetSubtargetInfo.h | 4 + llvm/include/llvm/DebugInfo/DWARF/DWARFDebugLoc.h | 9 +- llvm/include/llvm/IR/IRBuilder.h | 4 + llvm/include/llvm/IR/Instruction.def | 133 +- llvm/include/llvm/IR/Operator.h | 3 + llvm/include/llvm/IR/PatternMatch.h | 22 + llvm/include/llvm/MC/MCObjectFileInfo.h | 177 +- llvm/include/llvm/Object/ELFObjectFile.h | 2 + llvm/include/llvm/ProfileData/InstrProf.h | 2 +- llvm/include/llvm/Support/Automaton.h | 12 +- llvm/include/llvm/Support/TargetOpcodes.def | 2 +- llvm/include/llvm/Target/GenericOpcodes.td | 4 +- llvm/include/llvm/Transforms/Scalar/GVN.h | 23 +- .../include/llvm/Transforms/Scalar/JumpThreading.h | 3 + llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 12 +- llvm/lib/AsmParser/LLToken.h | 1 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 11 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 46 +- llvm/lib/CodeGen/AtomicExpandPass.cpp | 2 +- llvm/lib/CodeGen/DFAPacketizer.cpp | 62 +- llvm/lib/CodeGen/GlobalISel/CSEInfo.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 22 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 +- .../lib/CodeGen/GlobalISel/InstructionSelector.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 20 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 14 +- llvm/lib/CodeGen/HardwareLoops.cpp | 105 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 7 +- llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 24 + llvm/lib/CodeGen/MIRPrinter.cpp | 7 + llvm/lib/CodeGen/MachineInstr.cpp | 5 +- llvm/lib/CodeGen/MachineOutliner.cpp | 11 +- llvm/lib/CodeGen/MachineScheduler.cpp | 4 +- llvm/lib/CodeGen/MachineVerifier.cpp | 2 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 3 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 5 + .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 1 + llvm/lib/CodeGen/TargetLoweringBase.cpp | 1 + llvm/lib/CodeGen/TargetSubtargetInfo.cpp | 4 + llvm/lib/DebugInfo/DWARF/DWARFContext.cpp | 8 +- llvm/lib/DebugInfo/DWARF/DWARFDebugLoc.cpp | 9 +- llvm/lib/DebugInfo/DWARF/DWARFDie.cpp | 15 +- llvm/lib/IR/ConstantFold.cpp | 65 +- llvm/lib/IR/Core.cpp | 5 + llvm/lib/IR/Instruction.cpp | 1 + llvm/lib/IR/Instructions.cpp | 3 + llvm/lib/IR/Verifier.cpp | 3 + llvm/lib/Linker/IRMover.cpp | 29 +- llvm/lib/Support/Host.cpp | 29 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 2 +- .../Target/AArch64/AArch64InstructionSelector.cpp | 16 +- llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp | 6 +- .../lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 2 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 10 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 2 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 6 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 2 + .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 2 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 7 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 14 - llvm/lib/Target/ARM/ARM.td | 13 +- llvm/lib/Target/ARM/ARMCallLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 2 +- llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMSubtarget.cpp | 12 +- llvm/lib/Target/ARM/ARMSubtarget.h | 8 +- llvm/lib/Target/ARM/ARMTargetMachine.cpp | 16 +- llvm/lib/Target/ARM/ARMTargetMachine.h | 2 + llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp | 78 +- .../Hexagon/MCTargetDesc/HexagonMCCompound.cpp | 10 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 2 +- llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 +- llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 8 +- llvm/lib/Target/Mips/MipsLegalizerInfo.cpp | 2 +- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp | 4 +- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 55 + llvm/lib/Target/RISCV/RISCVInstrInfo.h | 8 + llvm/lib/Target/X86/X86CallLowering.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 22 +- llvm/lib/Target/X86/X86InstructionSelector.cpp | 6 +- llvm/lib/Target/X86/X86LegalizerInfo.cpp | 8 +- llvm/lib/Target/X86/X86MCInstLower.cpp | 46 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 21 + .../Transforms/InstCombine/InstCombineShifts.cpp | 35 +- llvm/lib/Transforms/ObjCARC/ObjCARCOpts.cpp | 29 +- llvm/lib/Transforms/Scalar/GVN.cpp | 7 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 216 +- llvm/lib/Transforms/Scalar/NewGVN.cpp | 18 +- llvm/lib/Transforms/Utils/LoopRotationUtils.cpp | 19 +- .../Vectorize/LoopVectorizationPlanner.h | 9 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 203 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 17 +- llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h | 44 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 23 +- llvm/lib/Transforms/Vectorize/VPlan.h | 16 + llvm/test/Analysis/CostModel/X86/reduce-and.ll | 42 +- llvm/test/Analysis/CostModel/X86/reduce-or.ll | 42 +- llvm/test/Bindings/OCaml/core.ml | 3 + llvm/test/Bindings/llvm-c/echo.ll | 1 + llvm/test/Bindings/llvm-c/freeze.ll | 22 + llvm/test/Bitcode/compatibility.ll | 14 +- .../AArch64/GlobalISel/arm64-irtranslator-gep.ll | 10 +- .../GlobalISel/arm64-irtranslator-switch.ll | 4 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 80 +- .../AArch64/GlobalISel/call-translator-cse.ll | 6 +- .../AArch64/GlobalISel/call-translator-ios.ll | 10 +- .../CodeGen/AArch64/GlobalISel/call-translator.ll | 26 +- .../GlobalISel/combiner-load-store-indexing.ll | 20 +- .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 64 +- .../CodeGen/AArch64/GlobalISel/inline-memmove.mir | 20 +- .../CodeGen/AArch64/GlobalISel/inline-memset.mir | 8 +- .../AArch64/GlobalISel/inline-small-memcpy.mir | 4 +- .../AArch64/GlobalISel/irtranslator-exceptions.ll | 4 +- .../GlobalISel/legalize-non-pow2-load-store.mir | 4 +- .../GlobalISel/legalize-phi-insertpt-decrement.mir | 8 +- .../{legalize-gep.mir => legalize-ptr-add.mir} | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-vaarg.mir | 8 +- .../GlobalISel/legalizer-info-validation.mir | 2 +- .../AArch64/GlobalISel/load-addressing-modes.mir | 44 +- .../CodeGen/AArch64/GlobalISel/select-load.mir | 16 +- .../CodeGen/AArch64/GlobalISel/select-store.mir | 12 +- llvm/test/CodeGen/AArch64/GlobalISel/select.mir | 6 +- .../AArch64/GlobalISel/store-addressing-modes.mir | 14 +- .../CodeGen/AArch64/GlobalISel/translate-gep.ll | 16 +- .../test/CodeGen/AArch64/merge-store-dependency.ll | 46 +- .../CodeGen/AMDGPU/GlobalISel/function-returns.ll | 8 +- .../inst-select-amdgpu-atomic-cmpxchg-flat.mir | 6 +- .../inst-select-atomic-cmpxchg-local.mir | 2 +- .../inst-select-atomicrmw-fadd-local.mir | 2 +- .../inst-select-atomicrmw-xchg-local.mir | 2 +- .../GlobalISel/inst-select-load-atomic-flat.mir | 4 +- .../GlobalISel/inst-select-load-atomic-global.mir | 8 +- .../GlobalISel/inst-select-load-atomic-local.mir | 2 +- .../GlobalISel/inst-select-load-constant.mir | 10 +- .../AMDGPU/GlobalISel/inst-select-load-flat.mir | 24 +- .../AMDGPU/GlobalISel/inst-select-load-global.mir | 24 +- .../AMDGPU/GlobalISel/inst-select-load-local.mir | 8 +- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 30 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 20 +- ...inst-select-gep.mir => inst-select-ptr-add.mir} | 16 +- .../AMDGPU/GlobalISel/inst-select-store-flat.mir | 2 +- .../AMDGPU/GlobalISel/inst-select-store-global.mir | 2 +- .../GlobalISel/inst-select-store-private.mir | 2 +- .../GlobalISel/irtranslator-amdgpu_kernel.ll | 152 +- .../GlobalISel/irtranslator-function-args.ll | 14 +- .../AMDGPU/GlobalISel/legalize-addrspacecast.mir | 8 +- .../GlobalISel/legalize-load-constant-32bit.mir | 6 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 2770 ++++++++++---------- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 2390 ++++++++--------- .../AMDGPU/GlobalISel/legalize-load-global.mir | 2452 ++++++++--------- .../AMDGPU/GlobalISel/legalize-load-local.mir | 2730 +++++++++---------- .../AMDGPU/GlobalISel/legalize-load-private.mir | 2760 +++++++++---------- .../CodeGen/AMDGPU/GlobalISel/legalize-phi.mir | 20 +- .../{legalize-gep.mir => legalize-ptr-add.mir} | 28 +- .../CodeGen/AMDGPU/GlobalISel/legalize-store.mir | 12 +- .../AMDGPU/GlobalISel/regbankselect-load.mir | 32 +- ...ankselect-gep.mir => regbankselect-ptr-add.mir} | 20 +- .../ARM/GlobalISel/arm-instruction-select.mir | 2 +- .../CodeGen/ARM/GlobalISel/arm-irtranslator.ll | 2 +- .../ARM/GlobalISel/arm-legalize-load-store.mir | 16 +- .../CodeGen/ARM/GlobalISel/arm-legalize-vfp4.mir | 4 +- .../CodeGen/ARM/GlobalISel/arm-param-lowering.ll | 36 +- .../CodeGen/ARM/GlobalISel/arm-regbankselect.mir | 4 +- .../GlobalISel/irtranslator-varargs-lowering.ll | 8 +- .../ARM/GlobalISel/thumb-select-load-store.mir | 2 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 4 + .../CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll | 2 +- llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll | 2 +- .../CodeGen/ARM/cortex-a57-misched-stm-wrback.ll | 2 +- llvm/test/CodeGen/ARM/cortex-a57-misched-stm.ll | 2 +- .../CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll | 2 +- llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll | 2 +- .../CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll | 2 +- llvm/test/CodeGen/ARM/cortex-a57-misched-vstm.ll | 2 +- llvm/test/CodeGen/ARM/memcpy-ldm-stm.ll | 8 +- llvm/test/CodeGen/ARM/postrasched.ll | 30 + llvm/test/CodeGen/ARM/thumb1_return_sequence.ll | 4 +- llvm/test/CodeGen/ARM/useaa.ll | 2 +- llvm/test/CodeGen/ARM/va_arg.ll | 51 +- .../CodeGen/BPF/CORE/field-reloc-bitfield-1.ll | 126 + .../CodeGen/BPF/CORE/field-reloc-bitfield-2.ll | 124 + .../CodeGen/MIR/X86/instr-heap-alloc-operands.mir | 42 + .../instruction-select/load_store_fold.mir | 16 +- .../GlobalISel/instruction-select/stack_args.mir | 2 +- .../Mips/GlobalISel/instruction-select/var_arg.mir | 2 +- .../irtranslator/aggregate_struct_return.ll | 12 +- .../Mips/GlobalISel/irtranslator/extend_args.ll | 12 +- .../Mips/GlobalISel/irtranslator/sret_pointer.ll | 2 +- .../Mips/GlobalISel/irtranslator/stack_args.ll | 2 +- .../Mips/GlobalISel/irtranslator/var_arg.ll | 2 +- .../Mips/GlobalISel/legalizer/dyn_stackalloc.mir | 4 +- .../Mips/GlobalISel/legalizer/stack_args.mir | 4 +- .../CodeGen/Mips/GlobalISel/legalizer/var_arg.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/load.mir | 2 +- .../regbankselect/long_ambiguous_chain_s32.mir | 18 +- .../regbankselect/long_ambiguous_chain_s64.mir | 18 +- .../Mips/GlobalISel/regbankselect/stack_args.mir | 4 +- .../Mips/GlobalISel/regbankselect/store.mir | 2 +- .../Mips/GlobalISel/regbankselect/var_arg.mir | 4 +- llvm/test/CodeGen/Mips/constraint-empty.ll | 14 + llvm/test/CodeGen/PowerPC/extract-and-store.ll | 24 +- llvm/test/CodeGen/PowerPC/f128-aggregates.ll | 4 +- llvm/test/CodeGen/PowerPC/instr-properties.ll | 9 + .../CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll | 32 +- .../CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll | 8 +- .../CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll | 24 +- llvm/test/CodeGen/RISCV/disjoint.ll | 26 + llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll | 103 + .../X86/GlobalISel/irtranslator-callingconv.ll | 40 +- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 4 +- .../{legalize-gep.mir => legalize-ptr-add.mir} | 16 +- .../test/CodeGen/X86/GlobalISel/legalize-undef.mir | 2 +- .../CodeGen/X86/GlobalISel/{gep.ll => ptr-add.ll} | 0 .../X86/GlobalISel/regbankselect-X86_64.mir | 12 +- .../GlobalISel/select-memop-scalar-unordered.mir | 4 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 4 +- .../{select-gep.mir => select-ptr-add.mir} | 2 +- .../x86_64-irtranslator-struct-return.ll | 12 +- llvm/test/CodeGen/X86/atomic-non-integer-fp128.ll | 9 +- llvm/test/CodeGen/X86/atomic-non-integer.ll | 202 +- llvm/test/CodeGen/X86/avx-intel-ocl.ll | 4 +- llvm/test/CodeGen/X86/avx512-mask-op.ll | 52 +- llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll | 16 +- llvm/test/CodeGen/X86/avx512-unsafe-fp-math.ll | 5 +- llvm/test/CodeGen/X86/avx512-vselect.ll | 2 +- llvm/test/CodeGen/X86/combineIncDecVector-crash.ll | 2 +- llvm/test/CodeGen/X86/exedepsfix-broadcast.ll | 2 +- llvm/test/CodeGen/X86/heap-alloc-markers.mir | 50 + llvm/test/CodeGen/X86/machine-combiner.ll | 12 +- llvm/test/CodeGen/X86/madd.ll | 4 +- llvm/test/CodeGen/X86/masked_compressstore.ll | 22 +- llvm/test/CodeGen/X86/masked_expandload.ll | 22 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 60 +- llvm/test/CodeGen/X86/pr29112.ll | 4 +- llvm/test/CodeGen/X86/sad.ll | 18 +- llvm/test/CodeGen/X86/sse-minmax.ll | 6 +- llvm/test/CodeGen/X86/stack-folding-fp-avx512.ll | 2 +- llvm/test/CodeGen/X86/uadd_sat_vec.ll | 4 +- llvm/test/CodeGen/X86/vec_umulo.ll | 24 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 18 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 44 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 8 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 18 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 34 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 8 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 24 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll | 4 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 4 +- llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll | 4 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 8 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 14 +- .../CodeGen/X86/vector-shift-by-select-loop.ll | 8 +- llvm/test/CodeGen/X86/vector-trunc-math.ll | 8 +- llvm/test/CodeGen/X86/vector-trunc-packus.ll | 4 +- llvm/test/CodeGen/X86/x86-interleaved-access.ll | 6 +- llvm/test/Linker/addrspace.ll | 12 + llvm/test/MC/Disassembler/AMDGPU/decode-err.txt | 4 + .../{test_g_gep.mir => test_g_ptr_add.mir} | 10 +- .../test/Transforms/HardwareLoops/ARM/structure.ll | 25 +- ...ift-input-masking-after-truncation-variant-a.ll | 24 +- ...ift-input-masking-after-truncation-variant-b.ll | 24 +- ...ift-input-masking-after-truncation-variant-c.ll | 24 +- ...ift-input-masking-after-truncation-variant-d.ll | 24 +- ...ift-input-masking-after-truncation-variant-e.ll | 24 +- ...ift-input-masking-after-truncation-variant-a.ll | 16 +- ...ift-input-masking-after-truncation-variant-b.ll | 16 +- ...ift-input-masking-after-truncation-variant-c.ll | 16 +- ...ift-input-masking-after-truncation-variant-d.ll | 16 +- ...ift-input-masking-after-truncation-variant-e.ll | 16 +- ...ift-input-masking-after-truncation-variant-f.ll | 16 +- llvm/test/Transforms/InstCombine/shift-logic.ll | 171 ++ .../Transforms/LoopUnroll/peel-loop-conditions.ll | 98 + llvm/test/Transforms/MergeFunc/inline-asm.ll | 6 +- llvm/test/Transforms/ObjCARC/post-inlining.ll | 64 + .../Transforms/SLPVectorizer/X86/reduction2.ll | 117 +- .../test/tools/llvm-dwarfdump/X86/debug_loclists.s | 120 + .../llvm-objcopy/ELF/basic-only-keep-debug.test | 22 - .../tools/llvm-objcopy/ELF/only-keep-debug.test | 224 ++ .../llvm-objdump/X86/elf-disassemble-bss.test | 37 + llvm/test/tools/llvm-profdata/show-prof-size.test | 2 +- llvm/tools/llvm-c-test/echo.cpp | 12 + llvm/tools/llvm-objcopy/CommonOpts.td | 5 +- llvm/tools/llvm-objcopy/ELF/ELFObjcopy.cpp | 21 +- llvm/tools/llvm-objcopy/ELF/Object.cpp | 115 +- llvm/tools/llvm-objcopy/ELF/Object.h | 52 +- llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 1 + llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 478 +--- llvm/utils/lit/lit/TestRunner.py | 94 +- llvm/utils/lit/lit/cl_arguments.py | 1 - llvm/utils/lit/lit/main.py | 13 +- llvm/utils/lit/lit/run.py | 5 +- .../Inputs/shtest-env/env-calls-not-builtin.txt | 4 + llvm/utils/lit/tests/Inputs/shtest-not/fail.py | 7 + llvm/utils/lit/tests/Inputs/shtest-not/lit.cfg | 7 + .../Inputs/shtest-not/not-args-last-is-crash.txt | 1 + .../Inputs/shtest-not/not-args-nested-none.txt | 1 + .../lit/tests/Inputs/shtest-not/not-args-none.txt | 1 + .../lit/tests/Inputs/shtest-not/not-calls-cd.txt | 3 + .../tests/Inputs/shtest-not/not-calls-colon.txt | 3 + .../shtest-not/not-calls-diff-with-crash.txt | 6 + .../lit/tests/Inputs/shtest-not/not-calls-diff.txt | 16 + .../lit/tests/Inputs/shtest-not/not-calls-echo.txt | 3 + .../Inputs/shtest-not/not-calls-env-builtin.txt | 4 + .../tests/Inputs/shtest-not/not-calls-export.txt | 3 + .../tests/Inputs/shtest-not/not-calls-external.txt | 66 + .../tests/Inputs/shtest-not/not-calls-mkdir.txt | 2 + .../lit/tests/Inputs/shtest-not/not-calls-rm.txt | 2 + llvm/utils/lit/tests/Inputs/shtest-not/pass.py | 5 + .../tests/Inputs/shtest-not/print_environment.py | 6 + llvm/utils/lit/tests/selecting.py | 19 +- llvm/utils/lit/tests/shtest-env.py | 9 +- llvm/utils/lit/tests/shtest-not.py | 115 + 405 files changed, 13127 insertions(+), 9507 deletions(-) create mode 100644 clang/test/CodeGen/mnop-mcount.c create mode 100644 clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu create mode 100644 clang/test/CodeGenCUDA/ms-linker-options.cu create mode 100644 clang/test/CodeGenOpenCL/fdeclare-opencl-builtins.cl create mode 100644 clang/test/Driver/hip-autolink.hip create mode 100644 lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.cpp create mode 100644 lldb/source/Plugins/ScriptInterpreter/Python/PythonReadline.h create mode 100644 lldb/test/Shell/Reproducer/Functionalities/Inputs/ExpressionEva [...] create mode 100644 lldb/test/Shell/Reproducer/Functionalities/TestExpressionEvalua [...] create mode 100644 llvm/docs/GlobalISel/GenericOpcode.rst create mode 100644 llvm/docs/GlobalISel/KnownBits.rst create mode 100644 llvm/docs/GlobalISel/block-extract.png create mode 100644 llvm/test/Bindings/llvm-c/freeze.ll rename llvm/test/CodeGen/AArch64/GlobalISel/{legalize-gep.mir => legalize-ptr-add. [...] rename llvm/test/CodeGen/AMDGPU/GlobalISel/{inst-select-gep.mir => inst-select-ptr [...] rename llvm/test/CodeGen/AMDGPU/GlobalISel/{legalize-gep.mir => legalize-ptr-add.m [...] rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-gep.mir => regbankselect [...] create mode 100644 llvm/test/CodeGen/ARM/postrasched.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-1.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/field-reloc-bitfield-2.ll create mode 100644 llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir create mode 100644 llvm/test/CodeGen/Mips/constraint-empty.ll create mode 100644 llvm/test/CodeGen/PowerPC/instr-properties.ll create mode 100644 llvm/test/CodeGen/RISCV/disjoint.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll rename llvm/test/CodeGen/X86/GlobalISel/{legalize-gep.mir => legalize-ptr-add.mir} (87%) rename llvm/test/CodeGen/X86/GlobalISel/{gep.ll => ptr-add.ll} (100%) rename llvm/test/CodeGen/X86/GlobalISel/{select-gep.mir => select-ptr-add.mir} (96%) create mode 100644 llvm/test/CodeGen/X86/heap-alloc-markers.mir create mode 100644 llvm/test/Linker/addrspace.ll create mode 100644 llvm/test/MC/Disassembler/AMDGPU/decode-err.txt rename llvm/test/MachineVerifier/{test_g_gep.mir => test_g_ptr_add.mir} (81%) create mode 100644 llvm/test/Transforms/InstCombine/shift-logic.ll create mode 100644 llvm/test/tools/llvm-dwarfdump/X86/debug_loclists.s delete mode 100644 llvm/test/tools/llvm-objcopy/ELF/basic-only-keep-debug.test create mode 100644 llvm/test/tools/llvm-objcopy/ELF/only-keep-debug.test create mode 100644 llvm/test/tools/llvm-objdump/X86/elf-disassemble-bss.test create mode 100644 llvm/utils/lit/tests/Inputs/shtest-env/env-calls-not-builtin.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/fail.py create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/lit.cfg create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-args-last-is-crash.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-args-nested-none.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-args-none.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-cd.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-colon.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-diff-with-crash.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-diff.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-echo.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-env-builtin.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-export.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-external.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-mkdir.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/not-calls-rm.txt create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/pass.py create mode 100644 llvm/utils/lit/tests/Inputs/shtest-not/print_environment.py create mode 100644 llvm/utils/lit/tests/shtest-not.py