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from 02685f635b [AArch64] Fix scalar vuqadd intrinsics operands new e7f2bc4f8f [RISCV] Specify registers used for exception handling

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Summary of changes: lib/Basic/Targets/RISCV.h | 9 +++++++++ test/CodeGen/builtins-riscv.c | 10 ++++++++++ 2 files changed, 19 insertions(+) create mode 100644 test/CodeGen/builtins-riscv.c