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from 458db9b6149 tree-optimization/111916 - SRA of BIT_FIELD_REF of constant [...] new 82bbbb73c67 RISC-V: Add popcount fallback expander. new 32b74c9e1d4 vect: Allow same precision for bit-precision conversions.

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Summary of changes: gcc/config/riscv/autovec.md | 14 + gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 71 + .../gcc.target/riscv/rvv/autovec/slp-mask-1.c | 18 + .../gcc.target/riscv/rvv/autovec/slp-mask-run-1.c | 31 + .../gcc.target/riscv/rvv/autovec/unop/popcount-1.c | 20 + .../gcc.target/riscv/rvv/autovec/unop/popcount-2.c | 19 + .../rvv/autovec/unop/popcount-run-1.c} | 9 +- .../gcc.target/riscv/rvv/autovec/unop/popcount.c | 1464 ++++++++++++++++++++ gcc/tree-vect-stmts.cc | 12 +- 10 files changed, 1649 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-mask-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount-2.c copy gcc/testsuite/gcc.target/{aarch64/sve/popcount_1_run.c => riscv/rvv/autovec/u [...] create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/popcount.c