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from b1ee91e Branch Folding: Accept explicit threshold for tail merge size. new f65766d RegScavenging: Add scavengeRegisterBackwards() new 3989d7e [SLP] Initialize VectorizedValue when gathering new 443f72b AMDGPU : Fix QSAD and MQSAD instructions' incorrect data type.

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Summary of changes: include/llvm/CodeGen/RegisterScavenging.h | 18 ++ include/llvm/IR/IntrinsicsAMDGPU.td | 4 +- lib/CodeGen/PrologEpilogInserter.cpp | 147 ++++++++------- lib/CodeGen/RegisterScavenging.cpp | 204 ++++++++++++++++----- lib/Target/AMDGPU/CIInstructions.td | 2 +- lib/Target/AMDGPU/SIInstrInfo.td | 1 + lib/Target/AMDGPU/SIInstructions.td | 2 +- lib/Transforms/Vectorize/SLPVectorizer.cpp | 74 +++++++- test/CodeGen/AMDGPU/captured-frame-index.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll | 18 +- test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll | 18 +- test/CodeGen/Mips/emergency-spill-slot-near-fp.ll | 88 ++++++--- test/CodeGen/PowerPC/dyn-alloca-aligned.ll | 4 +- test/CodeGen/Thumb/large-stack.ll | 4 +- .../SLPVectorizer/AArch64/gather-root.ll | 95 ++++++++++ 15 files changed, 509 insertions(+), 174 deletions(-) create mode 100644 test/Transforms/SLPVectorizer/AArch64/gather-root.ll