This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch master in repository llvm.

from c4071bcc5b6 [Hexagon] Return 0 from getDotNewPredOp when .new opcode do [...] new 9c2941a24ca [mips][microMIPS] Extending size reduction pass with LBU16, [...] new 48e0515b4f2 [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.

The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- lib/Target/Mips/MicroMipsSizeReduction.cpp | 57 ++++++++++++++++++++++ test/CodeGen/AMDGPU/basic-branch.ll | 2 - test/CodeGen/AMDGPU/branch-condition-and.ll | 3 +- test/CodeGen/AMDGPU/branch-relaxation.ll | 2 - test/CodeGen/AMDGPU/control-flow-fastregalloc.ll | 11 +---- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 9 ++-- test/CodeGen/AMDGPU/infinite-loop.ll | 2 +- .../AMDGPU/llvm.amdgcn.buffer.store.format.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll | 1 - test/CodeGen/AMDGPU/llvm.amdgcn.image.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll | 2 +- .../CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll | 4 +- test/CodeGen/AMDGPU/multi-divergent-exit-region.ll | 1 + test/CodeGen/AMDGPU/ret_jump.ll | 2 +- .../si-lower-control-flow-unreachable-block.ll | 3 -- test/CodeGen/AMDGPU/smrd-vccz-bug.ll | 2 +- test/CodeGen/AMDGPU/spill-m0.ll | 2 - test/CodeGen/AMDGPU/valu-i1.ll | 8 +-- .../micromips-lbu16-lhu16-sb16-sh16.ll | 40 +++++++++++++++ 24 files changed, 119 insertions(+), 46 deletions(-) create mode 100644 test/CodeGen/Mips/micromips-sizereduction/micromips-lbu16-lhu16 [...]