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from 7caa1ae5e45 RISC-V: Add RVV misc intrinsic support new 7e52f4420ff RISC-V: costs: miscomputed shiftadd_cost triggering synth_m [...]

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Summary of changes: gcc/config/riscv/riscv.cc | 3 ++- gcc/testsuite/gcc.target/riscv/pr108987.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr108987.c