This is an automated email from the git hooks/post-receive script.

unknown user pushed a change to branch master in repository llvm.

from 2d3fee0bf7a [ARM] Extract some code from ARMConstantIslandPass new 659a3204207 [ARM] Add ARMBasicBlockInfo.cpp new 82ad3d12cc5 [ARM] Remove ARMComputeBlockSize new f4bff34d4d8 Describe stack-id as an enum

The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: include/llvm/CodeGen/MIRYamlMapping.h | 18 ++- include/llvm/CodeGen/TargetFrameLowering.h | 19 +++ lib/CodeGen/MIRParser/MIRParser.cpp | 9 ++ lib/CodeGen/MIRPrinter.cpp | 5 +- lib/CodeGen/MachineFrameInfo.cpp | 4 +- lib/CodeGen/PrologEpilogInserter.cpp | 22 ++-- lib/Target/AMDGPU/SIDefines.h | 7 - lib/Target/AMDGPU/SIFrameLowering.cpp | 13 +- lib/Target/AMDGPU/SIFrameLowering.h | 2 + lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +- lib/Target/ARM/ARMBasicBlockInfo.cpp | 146 +++++++++++++++++++++ lib/Target/ARM/ARMComputeBlockSize.cpp | 80 ----------- .../AArch64/GlobalISel/arm64-irtranslator.ll | 6 +- .../AArch64/GlobalISel/arm64-regbankselect.mir | 2 +- test/CodeGen/AArch64/GlobalISel/call-translator.ll | 2 +- .../GlobalISel/fp128-legalize-crash-pr35690.mir | 2 +- .../AArch64/GlobalISel/select-gv-cmodel-large.mir | 2 +- .../AArch64/GlobalISel/select-gv-cmodel-tiny.mir | 2 +- test/CodeGen/AArch64/aarch64-mov-debug-locs.mir | 12 +- test/CodeGen/AArch64/branch-target-enforcment.mir | 4 +- test/CodeGen/AArch64/cfi_restore.mir | 4 +- .../dont-shrink-wrap-stack-mayloadorstore.mir | 4 +- test/CodeGen/AArch64/reverse-csr-restore-seq.mir | 2 +- test/CodeGen/AArch64/spill-stack-realignment.mir | 4 +- test/CodeGen/AArch64/stack-id-pei-alloc.mir | 20 +-- .../AArch64/stack-id-stackslot-scavenging.mir | 2 +- test/CodeGen/AArch64/wineh-frame5.mir | 2 +- test/CodeGen/AArch64/wineh-frame6.mir | 14 +- test/CodeGen/AArch64/wineh-frame7.mir | 14 +- test/CodeGen/AArch64/wineh-frame8.mir | 4 +- test/CodeGen/AArch64/wineh1.mir | 20 +-- test/CodeGen/AArch64/wineh2.mir | 30 ++--- test/CodeGen/AArch64/wineh3.mir | 28 ++-- test/CodeGen/AArch64/wineh4.mir | 28 ++-- test/CodeGen/AArch64/wineh5.mir | 20 +-- test/CodeGen/AArch64/wineh6.mir | 18 +-- test/CodeGen/AArch64/wineh7.mir | 14 +- test/CodeGen/AArch64/wineh8.mir | 28 ++-- test/CodeGen/AArch64/wineh_shrinkwrap.mir | 2 +- ...galizer-multiple-mem-operands-nontemporal-1.mir | 6 +- ...galizer-multiple-mem-operands-nontemporal-2.mir | 6 +- test/CodeGen/AMDGPU/sched-crash-dbg-value.mir | 2 +- test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir | 14 +- .../AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir | 4 +- .../AMDGPU/undefined-physreg-sgpr-spill.mir | 4 +- test/CodeGen/ARM/constant-island-movwt.mir | 20 +-- test/CodeGen/ARM/fp16-litpool-arm.mir | 2 +- test/CodeGen/ARM/fp16-litpool-thumb.mir | 4 +- test/CodeGen/ARM/fp16-litpool2-arm.mir | 2 +- test/CodeGen/ARM/fp16-litpool3-arm.mir | 2 +- test/CodeGen/ARM/register-scavenger-exceptions.mir | 6 +- test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir | 14 +- test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir | 14 +- .../MIR/AArch64/stack-object-local-offset.mir | 2 +- test/CodeGen/MIR/AMDGPU/stack-id.mir | 20 +-- test/CodeGen/MIR/X86/branch-folder-with-label.mir | 8 +- test/CodeGen/MIR/X86/diexpr-win32.mir | 10 +- test/CodeGen/MIR/X86/fixed-stack-di.mir | 2 +- test/CodeGen/MIR/X86/fixed-stack-objects.mir | 2 +- .../MIR/X86/spill-slot-fixed-stack-objects.mir | 2 +- test/CodeGen/MIR/X86/stack-objects.mir | 6 +- .../MIR/X86/variable-sized-stack-objects.mir | 4 +- .../GlobalISel/instruction-select/pointers.mir | 2 +- .../GlobalISel/instruction-select/stack_args.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 8 +- test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 8 +- .../CodeGen/Mips/GlobalISel/legalizer/pointers.mir | 2 +- .../Mips/GlobalISel/legalizer/stack_args.mir | 2 +- test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 8 +- .../Mips/GlobalISel/regbankselect/pointers.mir | 2 +- .../Mips/GlobalISel/regbankselect/stack_args.mir | 2 +- test/CodeGen/Mips/micromips-eva.mir | 2 +- test/CodeGen/Mips/micromips-short-delay-slot.mir | 2 +- .../micromips-sizereduction/micromips-lwp-swp.mir | 24 ++-- .../micromips-sizereduction/micromips-movep.mir | 4 +- .../micromips-no-lwp-swp.mir | 16 +-- .../PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir | 6 +- test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 10 +- test/CodeGen/PowerPC/setcr_bc.mir | 2 +- test/CodeGen/PowerPC/setcr_bc2.mir | 2 +- test/CodeGen/PowerPC/setcr_bc3.mir | 2 +- test/CodeGen/SystemZ/debuginstr-02.mir | 2 +- test/CodeGen/SystemZ/subregliveness-06.mir | 4 +- test/CodeGen/Thumb/PR36658.mir | 4 +- test/CodeGen/Thumb2/high-reg-spill.mir | 2 +- test/CodeGen/Thumb2/ifcvt-cbz.mir | 12 +- test/CodeGen/Thumb2/peephole-cmp.mir | 2 +- .../X86/GlobalISel/x32-select-frameIndex.mir | 2 +- .../X86/GlobalISel/x86-legalize-inttoptr.mir | 2 +- .../X86/GlobalISel/x86-legalize-ptrtoint.mir | 8 +- test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir | 12 +- test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir | 12 +- .../X86/GlobalISel/x86-select-frameIndex.mir | 2 +- .../CodeGen/X86/GlobalISel/x86-select-inttoptr.mir | 2 +- .../CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir | 8 +- test/CodeGen/X86/GlobalISel/x86-select-srem.mir | 12 +- test/CodeGen/X86/GlobalISel/x86-select-udiv.mir | 12 +- test/CodeGen/X86/GlobalISel/x86-select-urem.mir | 12 +- .../X86/GlobalISel/x86_64-select-frameIndex.mir | 2 +- test/CodeGen/X86/PR37310.mir | 4 +- test/CodeGen/X86/avoid-sfb-offset.mir | 4 +- test/CodeGen/X86/movtopush.mir | 6 +- test/CodeGen/X86/pr30821.mir | 6 +- test/CodeGen/X86/prologepilog_deref_size.mir | 2 +- test/CodeGen/X86/regalloc-copy-hints.mir | 2 +- test/CodeGen/X86/shrink_wrap_dbg_value.mir | 4 +- test/CodeGen/X86/win_coreclr_chkstk_liveins.mir | 2 +- test/DebugInfo/AArch64/asan-stack-vars.mir | 60 ++++----- .../AArch64/compiler-gen-bbs-livedebugvalues.mir | 6 +- test/DebugInfo/ARM/cfi-eof-prologue.mir | 8 +- .../MIR/ARM/live-debug-values-reg-copy.mir | 8 +- test/DebugInfo/MIR/Mips/last-inst-bundled.mir | 6 +- .../MIR/Mips/live-debug-values-reg-copy.mir | 8 +- test/DebugInfo/MIR/X86/dbg-stack-value-range.mir | 4 +- test/DebugInfo/MIR/X86/debug-loc-0.mir | 2 +- test/DebugInfo/MIR/X86/kill-after-spill.mir | 16 +-- .../MIR/X86/live-debug-values-reg-copy.mir | 6 +- .../MIR/X86/live-debug-values-restore.mir | 14 +- test/DebugInfo/X86/debug-loc-asan.mir | 22 ++-- test/DebugInfo/X86/debug-loc-offset.mir | 14 +- test/DebugInfo/X86/dw_op_minus.mir | 4 +- test/DebugInfo/X86/live-debug-vars-dse.mir | 2 +- test/DebugInfo/X86/pr19307.mir | 10 +- test/DebugInfo/X86/prolog-params.mir | 8 +- 124 files changed, 669 insertions(+), 552 deletions(-) create mode 100644 lib/Target/ARM/ARMBasicBlockInfo.cpp delete mode 100644 lib/Target/ARM/ARMComputeBlockSize.cpp